/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Intrinsic Function Source Fragment                                         *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifndef LLVM_IR_INTRINSIC_NVVM_ENUMS_H
#define LLVM_IR_INTRINSIC_NVVM_ENUMS_H
namespace llvm::Intrinsic {
enum NVVMIntrinsics : unsigned {
// Enum values for intrinsics.
    nvvm_activemask = 8592,                           // llvm.nvvm.activemask (IntrinsicsNVVM.td:2465)
    nvvm_add_rm_d,                             // llvm.nvvm.add.rm.d (IntrinsicsNVVM.td:1589)
    nvvm_add_rm_f,                             // llvm.nvvm.add.rm.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rm_ftz_f,                         // llvm.nvvm.add.rm.ftz.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rm_ftz_sat_f,                     // llvm.nvvm.add.rm.ftz.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rm_sat_f,                         // llvm.nvvm.add.rm.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rn_d,                             // llvm.nvvm.add.rn.d (IntrinsicsNVVM.td:1589)
    nvvm_add_rn_f,                             // llvm.nvvm.add.rn.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rn_ftz_f,                         // llvm.nvvm.add.rn.ftz.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rn_ftz_sat_f,                     // llvm.nvvm.add.rn.ftz.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rn_sat_f,                         // llvm.nvvm.add.rn.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rp_d,                             // llvm.nvvm.add.rp.d (IntrinsicsNVVM.td:1589)
    nvvm_add_rp_f,                             // llvm.nvvm.add.rp.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rp_ftz_f,                         // llvm.nvvm.add.rp.ftz.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rp_ftz_sat_f,                     // llvm.nvvm.add.rp.ftz.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rp_sat_f,                         // llvm.nvvm.add.rp.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rz_d,                             // llvm.nvvm.add.rz.d (IntrinsicsNVVM.td:1589)
    nvvm_add_rz_f,                             // llvm.nvvm.add.rz.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rz_ftz_f,                         // llvm.nvvm.add.rz.ftz.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rz_ftz_sat_f,                     // llvm.nvvm.add.rz.ftz.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_add_rz_sat_f,                         // llvm.nvvm.add.rz.sat.f (IntrinsicsNVVM.td:1585)
    nvvm_applypriority_L2_evict_normal,        // llvm.nvvm.applypriority.L2.evict.normal (IntrinsicsNVVM.td:2948)
    nvvm_applypriority_global_L2_evict_normal,  // llvm.nvvm.applypriority.global.L2.evict.normal (IntrinsicsNVVM.td:2945)
    nvvm_atomic_add_gen_f_cta,                 // llvm.nvvm.atomic.add.gen.f.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_add_gen_f_sys,                 // llvm.nvvm.atomic.add.gen.f.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_add_gen_i_cta,                 // llvm.nvvm.atomic.add.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_add_gen_i_sys,                 // llvm.nvvm.atomic.add.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_and_gen_i_cta,                 // llvm.nvvm.atomic.and.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_and_gen_i_sys,                 // llvm.nvvm.atomic.and.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_cas_gen_i_cta,                 // llvm.nvvm.atomic.cas.gen.i.cta (IntrinsicsNVVM.td:1836)
    nvvm_atomic_cas_gen_i_sys,                 // llvm.nvvm.atomic.cas.gen.i.sys (IntrinsicsNVVM.td:1837)
    nvvm_atomic_dec_gen_i_cta,                 // llvm.nvvm.atomic.dec.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_dec_gen_i_sys,                 // llvm.nvvm.atomic.dec.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_exch_gen_i_cta,                // llvm.nvvm.atomic.exch.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_exch_gen_i_sys,                // llvm.nvvm.atomic.exch.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_inc_gen_i_cta,                 // llvm.nvvm.atomic.inc.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_inc_gen_i_sys,                 // llvm.nvvm.atomic.inc.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_max_gen_i_cta,                 // llvm.nvvm.atomic.max.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_max_gen_i_sys,                 // llvm.nvvm.atomic.max.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_min_gen_i_cta,                 // llvm.nvvm.atomic.min.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_min_gen_i_sys,                 // llvm.nvvm.atomic.min.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_or_gen_i_cta,                  // llvm.nvvm.atomic.or.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_or_gen_i_sys,                  // llvm.nvvm.atomic.or.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_atomic_xor_gen_i_cta,                 // llvm.nvvm.atomic.xor.gen.i.cta (IntrinsicsNVVM.td:1832)
    nvvm_atomic_xor_gen_i_sys,                 // llvm.nvvm.atomic.xor.gen.i.sys (IntrinsicsNVVM.td:1833)
    nvvm_bar_warp_sync,                        // llvm.nvvm.bar.warp.sync (IntrinsicsNVVM.td:1857)
    nvvm_barrier_cluster_arrive,               // llvm.nvvm.barrier.cluster.arrive (IntrinsicsNVVM.td:1888)
    nvvm_barrier_cluster_arrive_aligned,       // llvm.nvvm.barrier.cluster.arrive.aligned (IntrinsicsNVVM.td:1893)
    nvvm_barrier_cluster_arrive_relaxed,       // llvm.nvvm.barrier.cluster.arrive.relaxed (IntrinsicsNVVM.td:1889)
    nvvm_barrier_cluster_arrive_relaxed_aligned,  // llvm.nvvm.barrier.cluster.arrive.relaxed.aligned (IntrinsicsNVVM.td:1894)
    nvvm_barrier_cluster_wait,                 // llvm.nvvm.barrier.cluster.wait (IntrinsicsNVVM.td:1890)
    nvvm_barrier_cluster_wait_aligned,         // llvm.nvvm.barrier.cluster.wait.aligned (IntrinsicsNVVM.td:1895)
    nvvm_barrier_cta_arrive_aligned_count,     // llvm.nvvm.barrier.cta.arrive.aligned.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_arrive_count,             // llvm.nvvm.barrier.cta.arrive.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_and_aligned_all,      // llvm.nvvm.barrier.cta.red.and.aligned.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_and_aligned_count,    // llvm.nvvm.barrier.cta.red.and.aligned.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_and_all,              // llvm.nvvm.barrier.cta.red.and.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_and_count,            // llvm.nvvm.barrier.cta.red.and.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_or_aligned_all,       // llvm.nvvm.barrier.cta.red.or.aligned.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_or_aligned_count,     // llvm.nvvm.barrier.cta.red.or.aligned.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_or_all,               // llvm.nvvm.barrier.cta.red.or.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_or_count,             // llvm.nvvm.barrier.cta.red.or.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_popc_aligned_all,     // llvm.nvvm.barrier.cta.red.popc.aligned.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_popc_aligned_count,   // llvm.nvvm.barrier.cta.red.popc.aligned.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_red_popc_all,             // llvm.nvvm.barrier.cta.red.popc.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_red_popc_count,           // llvm.nvvm.barrier.cta.red.popc.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_sync_aligned_all,         // llvm.nvvm.barrier.cta.sync.aligned.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_sync_aligned_count,       // llvm.nvvm.barrier.cta.sync.aligned.count (IntrinsicsNVVM.td:1865)
    nvvm_barrier_cta_sync_all,                 // llvm.nvvm.barrier.cta.sync.all (IntrinsicsNVVM.td:1868)
    nvvm_barrier_cta_sync_count,               // llvm.nvvm.barrier.cta.sync.count (IntrinsicsNVVM.td:1865)
    nvvm_bf16x2_to_ue8m0x2_rp,                 // llvm.nvvm.bf16x2.to.ue8m0x2.rp (IntrinsicsNVVM.td:1810)
    nvvm_bf16x2_to_ue8m0x2_rp_satfinite,       // llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite (IntrinsicsNVVM.td:1810)
    nvvm_bf16x2_to_ue8m0x2_rz,                 // llvm.nvvm.bf16x2.to.ue8m0x2.rz (IntrinsicsNVVM.td:1810)
    nvvm_bf16x2_to_ue8m0x2_rz_satfinite,       // llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite (IntrinsicsNVVM.td:1810)
    nvvm_bf2h_rn,                              // llvm.nvvm.bf2h.rn (IntrinsicsNVVM.td:1701)
    nvvm_bf2h_rn_ftz,                          // llvm.nvvm.bf2h.rn.ftz (IntrinsicsNVVM.td:1701)
    nvvm_bmsk_clamp,                           // llvm.nvvm.bmsk.clamp (IntrinsicsNVVM.td:1637)
    nvvm_bmsk_wrap,                            // llvm.nvvm.bmsk.wrap (IntrinsicsNVVM.td:1637)
    nvvm_ceil_d,                               // llvm.nvvm.ceil.d (IntrinsicsNVVM.td:1417)
    nvvm_ceil_f,                               // llvm.nvvm.ceil.f (IntrinsicsNVVM.td:1415)
    nvvm_ceil_ftz_f,                           // llvm.nvvm.ceil.ftz.f (IntrinsicsNVVM.td:1415)
    nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x,  // llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.x (IntrinsicsNVVM.td:3187)
    nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y,  // llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.y (IntrinsicsNVVM.td:3187)
    nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z,  // llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.z (IntrinsicsNVVM.td:3187)
    nvvm_clusterlaunchcontrol_query_cancel_is_canceled,  // llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled (IntrinsicsNVVM.td:3182)
    nvvm_clusterlaunchcontrol_try_cancel_async_multicast_shared,  // llvm.nvvm.clusterlaunchcontrol.try_cancel.async.multicast.shared (IntrinsicsNVVM.td:3175)
    nvvm_clusterlaunchcontrol_try_cancel_async_shared,  // llvm.nvvm.clusterlaunchcontrol.try_cancel.async.shared (IntrinsicsNVVM.td:3170)
    nvvm_compiler_error,                       // llvm.nvvm.compiler.error (IntrinsicsNVVM.td:2151)
    nvvm_compiler_warn,                        // llvm.nvvm.compiler.warn (IntrinsicsNVVM.td:2152)
    nvvm_cos_approx_f,                         // llvm.nvvm.cos.approx.f (IntrinsicsNVVM.td:1487)
    nvvm_cos_approx_ftz_f,                     // llvm.nvvm.cos.approx.ftz.f (IntrinsicsNVVM.td:1487)
    nvvm_cp_async_bulk_commit_group,           // llvm.nvvm.cp.async.bulk.commit.group (IntrinsicsNVVM.td:1992)
    nvvm_cp_async_bulk_global_to_shared_cluster,  // llvm.nvvm.cp.async.bulk.global.to.shared.cluster (IntrinsicsNVVM.td:2960)
    nvvm_cp_async_bulk_global_to_shared_cta,   // llvm.nvvm.cp.async.bulk.global.to.shared.cta (IntrinsicsNVVM.td:2974)
    nvvm_cp_async_bulk_prefetch_L2,            // llvm.nvvm.cp.async.bulk.prefetch.L2 (IntrinsicsNVVM.td:3020)
    nvvm_cp_async_bulk_shared_cta_to_cluster,  // llvm.nvvm.cp.async.bulk.shared.cta.to.cluster (IntrinsicsNVVM.td:2986)
    nvvm_cp_async_bulk_shared_cta_to_global,   // llvm.nvvm.cp.async.bulk.shared.cta.to.global (IntrinsicsNVVM.td:2996)
    nvvm_cp_async_bulk_shared_cta_to_global_bytemask,  // llvm.nvvm.cp.async.bulk.shared.cta.to.global.bytemask (IntrinsicsNVVM.td:3007)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.3d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.4d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.5d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_128_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.128.3d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_128_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.128.4d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_128_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.128.5d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.3d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.4d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_im2col_w_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.im2col.w.5d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.1d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.2d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.3d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.4d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.5d (IntrinsicsNVVM.td:2874)
    nvvm_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.cta.tile.gather4.2d (IntrinsicsNVVM.td:2905)
    nvvm_cp_async_bulk_tensor_g2s_im2col_3d,   // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.3d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_4d,   // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.4d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_5d,   // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.5d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_128_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.128.3d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_128_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.128.4d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_128_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.128.5d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_3d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.3d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_4d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.4d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_im2col_w_5d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.w.5d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_1d,     // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_2d,     // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_3d,     // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_4d,     // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.4d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_5d,     // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.5d (IntrinsicsNVVM.td:2862)
    nvvm_cp_async_bulk_tensor_g2s_tile_gather4_2d,  // llvm.nvvm.cp.async.bulk.tensor.g2s.tile.gather4.2d (IntrinsicsNVVM.td:2888)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.3d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.4d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.5d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_128_3d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.128.3d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_128_4d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.128.4d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_128_5d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.128.5d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_3d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.3d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_4d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.4d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_im2col_w_5d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.im2col.w.5d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.1d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.2d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.3d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.4d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.5d (IntrinsicsNVVM.td:2865)
    nvvm_cp_async_bulk_tensor_prefetch_tile_gather4_2d,  // llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d (IntrinsicsNVVM.td:2918)
    nvvm_cp_async_bulk_tensor_reduce_add_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_add_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.add.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_and_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.and.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_dec_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.dec.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_inc_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.inc.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_max_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.max.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_min_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.min.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_or_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.or.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_im2col_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.im2col.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_im2col_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.im2col.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_im2col_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.im2col.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_tile_1d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.tile.1d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_tile_2d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.tile.2d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_tile_3d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.tile.3d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_tile_4d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.tile.4d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_reduce_xor_tile_5d,  // llvm.nvvm.cp.async.bulk.tensor.reduce.xor.tile.5d (IntrinsicsNVVM.td:2810)
    nvvm_cp_async_bulk_tensor_s2g_im2col_3d,   // llvm.nvvm.cp.async.bulk.tensor.s2g.im2col.3d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_im2col_4d,   // llvm.nvvm.cp.async.bulk.tensor.s2g.im2col.4d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_im2col_5d,   // llvm.nvvm.cp.async.bulk.tensor.s2g.im2col.5d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_1d,     // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.1d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_2d,     // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.2d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_3d,     // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.3d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_4d,     // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.4d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_5d,     // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.5d (IntrinsicsNVVM.td:2799)
    nvvm_cp_async_bulk_tensor_s2g_tile_scatter4_2d,  // llvm.nvvm.cp.async.bulk.tensor.s2g.tile.scatter4.2d (IntrinsicsNVVM.td:2822)
    nvvm_cp_async_bulk_wait_group,             // llvm.nvvm.cp.async.bulk.wait.group (IntrinsicsNVVM.td:1994)
    nvvm_cp_async_bulk_wait_group_read,        // llvm.nvvm.cp.async.bulk.wait.group.read (IntrinsicsNVVM.td:1997)
    nvvm_cp_async_ca_shared_global_16,         // llvm.nvvm.cp.async.ca.shared.global.16 (IntrinsicsNVVM.td:1974)
    nvvm_cp_async_ca_shared_global_16_s,       // llvm.nvvm.cp.async.ca.shared.global.16.s (IntrinsicsNVVM.td:1975)
    nvvm_cp_async_ca_shared_global_4,          // llvm.nvvm.cp.async.ca.shared.global.4 (IntrinsicsNVVM.td:1974)
    nvvm_cp_async_ca_shared_global_4_s,        // llvm.nvvm.cp.async.ca.shared.global.4.s (IntrinsicsNVVM.td:1975)
    nvvm_cp_async_ca_shared_global_8,          // llvm.nvvm.cp.async.ca.shared.global.8 (IntrinsicsNVVM.td:1974)
    nvvm_cp_async_ca_shared_global_8_s,        // llvm.nvvm.cp.async.ca.shared.global.8.s (IntrinsicsNVVM.td:1975)
    nvvm_cp_async_cg_shared_global_16,         // llvm.nvvm.cp.async.cg.shared.global.16 (IntrinsicsNVVM.td:1974)
    nvvm_cp_async_cg_shared_global_16_s,       // llvm.nvvm.cp.async.cg.shared.global.16.s (IntrinsicsNVVM.td:1975)
    nvvm_cp_async_commit_group,                // llvm.nvvm.cp.async.commit.group (IntrinsicsNVVM.td:1984)
    nvvm_cp_async_mbarrier_arrive,             // llvm.nvvm.cp.async.mbarrier.arrive (IntrinsicsNVVM.td:1961)
    nvvm_cp_async_mbarrier_arrive_noinc,       // llvm.nvvm.cp.async.mbarrier.arrive.noinc (IntrinsicsNVVM.td:1965)
    nvvm_cp_async_mbarrier_arrive_noinc_shared,  // llvm.nvvm.cp.async.mbarrier.arrive.noinc.shared (IntrinsicsNVVM.td:1967)
    nvvm_cp_async_mbarrier_arrive_shared,      // llvm.nvvm.cp.async.mbarrier.arrive.shared (IntrinsicsNVVM.td:1963)
    nvvm_cp_async_wait_all,                    // llvm.nvvm.cp.async.wait.all (IntrinsicsNVVM.td:1989)
    nvvm_cp_async_wait_group,                  // llvm.nvvm.cp.async.wait.group (IntrinsicsNVVM.td:1986)
    nvvm_d2f_rm,                               // llvm.nvvm.d2f.rm (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rm_ftz,                           // llvm.nvvm.d2f.rm.ftz (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rn,                               // llvm.nvvm.d2f.rn (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rn_ftz,                           // llvm.nvvm.d2f.rn.ftz (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rp,                               // llvm.nvvm.d2f.rp (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rp_ftz,                           // llvm.nvvm.d2f.rp.ftz (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rz,                               // llvm.nvvm.d2f.rz (IntrinsicsNVVM.td:1663)
    nvvm_d2f_rz_ftz,                           // llvm.nvvm.d2f.rz.ftz (IntrinsicsNVVM.td:1663)
    nvvm_d2i_hi,                               // llvm.nvvm.d2i.hi (IntrinsicsNVVM.td:1658)
    nvvm_d2i_lo,                               // llvm.nvvm.d2i.lo (IntrinsicsNVVM.td:1656)
    nvvm_d2i_rm,                               // llvm.nvvm.d2i.rm (IntrinsicsNVVM.td:1668)
    nvvm_d2i_rn,                               // llvm.nvvm.d2i.rn (IntrinsicsNVVM.td:1668)
    nvvm_d2i_rp,                               // llvm.nvvm.d2i.rp (IntrinsicsNVVM.td:1668)
    nvvm_d2i_rz,                               // llvm.nvvm.d2i.rz (IntrinsicsNVVM.td:1668)
    nvvm_d2ll_rm,                              // llvm.nvvm.d2ll.rm (IntrinsicsNVVM.td:1685)
    nvvm_d2ll_rn,                              // llvm.nvvm.d2ll.rn (IntrinsicsNVVM.td:1685)
    nvvm_d2ll_rp,                              // llvm.nvvm.d2ll.rp (IntrinsicsNVVM.td:1685)
    nvvm_d2ll_rz,                              // llvm.nvvm.d2ll.rz (IntrinsicsNVVM.td:1685)
    nvvm_d2ui_rm,                              // llvm.nvvm.d2ui.rm (IntrinsicsNVVM.td:1668)
    nvvm_d2ui_rn,                              // llvm.nvvm.d2ui.rn (IntrinsicsNVVM.td:1668)
    nvvm_d2ui_rp,                              // llvm.nvvm.d2ui.rp (IntrinsicsNVVM.td:1668)
    nvvm_d2ui_rz,                              // llvm.nvvm.d2ui.rz (IntrinsicsNVVM.td:1668)
    nvvm_d2ull_rm,                             // llvm.nvvm.d2ull.rm (IntrinsicsNVVM.td:1685)
    nvvm_d2ull_rn,                             // llvm.nvvm.d2ull.rn (IntrinsicsNVVM.td:1685)
    nvvm_d2ull_rp,                             // llvm.nvvm.d2ull.rp (IntrinsicsNVVM.td:1685)
    nvvm_d2ull_rz,                             // llvm.nvvm.d2ull.rz (IntrinsicsNVVM.td:1685)
    nvvm_discard_L2,                           // llvm.nvvm.discard.L2 (IntrinsicsNVVM.td:2955)
    nvvm_discard_global_L2,                    // llvm.nvvm.discard.global.L2 (IntrinsicsNVVM.td:2954)
    nvvm_div_approx_f,                         // llvm.nvvm.div.approx.f (IntrinsicsNVVM.td:1379)
    nvvm_div_approx_ftz_f,                     // llvm.nvvm.div.approx.ftz.f (IntrinsicsNVVM.td:1379)
    nvvm_div_full,                             // llvm.nvvm.div.full (IntrinsicsNVVM.td:1382)
    nvvm_div_full_ftz,                         // llvm.nvvm.div.full.ftz (IntrinsicsNVVM.td:1382)
    nvvm_div_rm_d,                             // llvm.nvvm.div.rm.d (IntrinsicsNVVM.td:1391)
    nvvm_div_rm_f,                             // llvm.nvvm.div.rm.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rm_ftz_f,                         // llvm.nvvm.div.rm.ftz.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rn_d,                             // llvm.nvvm.div.rn.d (IntrinsicsNVVM.td:1391)
    nvvm_div_rn_f,                             // llvm.nvvm.div.rn.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rn_ftz_f,                         // llvm.nvvm.div.rn.ftz.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rp_d,                             // llvm.nvvm.div.rp.d (IntrinsicsNVVM.td:1391)
    nvvm_div_rp_f,                             // llvm.nvvm.div.rp.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rp_ftz_f,                         // llvm.nvvm.div.rp.ftz.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rz_d,                             // llvm.nvvm.div.rz.d (IntrinsicsNVVM.td:1391)
    nvvm_div_rz_f,                             // llvm.nvvm.div.rz.f (IntrinsicsNVVM.td:1388)
    nvvm_div_rz_ftz_f,                         // llvm.nvvm.div.rz.ftz.f (IntrinsicsNVVM.td:1388)
    nvvm_e2m1x2_to_f16x2_rn,                   // llvm.nvvm.e2m1x2.to.f16x2.rn (IntrinsicsNVVM.td:1772)
    nvvm_e2m1x2_to_f16x2_rn_relu,              // llvm.nvvm.e2m1x2.to.f16x2.rn.relu (IntrinsicsNVVM.td:1772)
    nvvm_e2m3x2_to_f16x2_rn,                   // llvm.nvvm.e2m3x2.to.f16x2.rn (IntrinsicsNVVM.td:1789)
    nvvm_e2m3x2_to_f16x2_rn_relu,              // llvm.nvvm.e2m3x2.to.f16x2.rn.relu (IntrinsicsNVVM.td:1789)
    nvvm_e3m2x2_to_f16x2_rn,                   // llvm.nvvm.e3m2x2.to.f16x2.rn (IntrinsicsNVVM.td:1789)
    nvvm_e3m2x2_to_f16x2_rn_relu,              // llvm.nvvm.e3m2x2.to.f16x2.rn.relu (IntrinsicsNVVM.td:1789)
    nvvm_e4m3x2_to_f16x2_rn,                   // llvm.nvvm.e4m3x2.to.f16x2.rn (IntrinsicsNVVM.td:1753)
    nvvm_e4m3x2_to_f16x2_rn_relu,              // llvm.nvvm.e4m3x2.to.f16x2.rn.relu (IntrinsicsNVVM.td:1753)
    nvvm_e5m2x2_to_f16x2_rn,                   // llvm.nvvm.e5m2x2.to.f16x2.rn (IntrinsicsNVVM.td:1753)
    nvvm_e5m2x2_to_f16x2_rn_relu,              // llvm.nvvm.e5m2x2.to.f16x2.rn.relu (IntrinsicsNVVM.td:1753)
    nvvm_elect_sync,                           // llvm.nvvm.elect.sync (IntrinsicsNVVM.td:2495)
    nvvm_ex2_approx,                           // llvm.nvvm.ex2.approx (IntrinsicsNVVM.td:1471)
    nvvm_ex2_approx_ftz,                       // llvm.nvvm.ex2.approx.ftz (IntrinsicsNVVM.td:1471)
    nvvm_exit,                                 // llvm.nvvm.exit (IntrinsicsNVVM.td:2779)
    nvvm_f16x2_to_e4m3x2_rn,                   // llvm.nvvm.f16x2.to.e4m3x2.rn (IntrinsicsNVVM.td:1750)
    nvvm_f16x2_to_e4m3x2_rn_relu,              // llvm.nvvm.f16x2.to.e4m3x2.rn.relu (IntrinsicsNVVM.td:1750)
    nvvm_f16x2_to_e5m2x2_rn,                   // llvm.nvvm.f16x2.to.e5m2x2.rn (IntrinsicsNVVM.td:1750)
    nvvm_f16x2_to_e5m2x2_rn_relu,              // llvm.nvvm.f16x2.to.e5m2x2.rn.relu (IntrinsicsNVVM.td:1750)
    nvvm_f2bf16_rn,                            // llvm.nvvm.f2bf16.rn (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rn_relu,                       // llvm.nvvm.f2bf16.rn.relu (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rn_relu_satfinite,             // llvm.nvvm.f2bf16.rn.relu.satfinite (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rn_satfinite,                  // llvm.nvvm.f2bf16.rn.satfinite (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rz,                            // llvm.nvvm.f2bf16.rz (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rz_relu,                       // llvm.nvvm.f2bf16.rz.relu (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rz_relu_satfinite,             // llvm.nvvm.f2bf16.rz.relu.satfinite (IntrinsicsNVVM.td:1714)
    nvvm_f2bf16_rz_satfinite,                  // llvm.nvvm.f2bf16.rz.satfinite (IntrinsicsNVVM.td:1714)
    nvvm_f2f16_rn,                             // llvm.nvvm.f2f16.rn (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rn_relu,                        // llvm.nvvm.f2f16.rn.relu (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rn_relu_satfinite,              // llvm.nvvm.f2f16.rn.relu.satfinite (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rn_satfinite,                   // llvm.nvvm.f2f16.rn.satfinite (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rz,                             // llvm.nvvm.f2f16.rz (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rz_relu,                        // llvm.nvvm.f2f16.rz.relu (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rz_relu_satfinite,              // llvm.nvvm.f2f16.rz.relu.satfinite (IntrinsicsNVVM.td:1717)
    nvvm_f2f16_rz_satfinite,                   // llvm.nvvm.f2f16.rz.satfinite (IntrinsicsNVVM.td:1717)
    nvvm_f2h_rn,                               // llvm.nvvm.f2h.rn (IntrinsicsNVVM.td:1698)
    nvvm_f2h_rn_ftz,                           // llvm.nvvm.f2h.rn.ftz (IntrinsicsNVVM.td:1698)
    nvvm_f2i_rm,                               // llvm.nvvm.f2i.rm (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rm_ftz,                           // llvm.nvvm.f2i.rm.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rn,                               // llvm.nvvm.f2i.rn (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rn_ftz,                           // llvm.nvvm.f2i.rn.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rp,                               // llvm.nvvm.f2i.rp (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rp_ftz,                           // llvm.nvvm.f2i.rp.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rz,                               // llvm.nvvm.f2i.rz (IntrinsicsNVVM.td:1675)
    nvvm_f2i_rz_ftz,                           // llvm.nvvm.f2i.rz.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2ll_rm,                              // llvm.nvvm.f2ll.rm (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rm_ftz,                          // llvm.nvvm.f2ll.rm.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rn,                              // llvm.nvvm.f2ll.rn (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rn_ftz,                          // llvm.nvvm.f2ll.rn.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rp,                              // llvm.nvvm.f2ll.rp (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rp_ftz,                          // llvm.nvvm.f2ll.rp.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rz,                              // llvm.nvvm.f2ll.rz (IntrinsicsNVVM.td:1682)
    nvvm_f2ll_rz_ftz,                          // llvm.nvvm.f2ll.rz.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2tf32_rn,                            // llvm.nvvm.f2tf32.rn (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rn_relu,                       // llvm.nvvm.f2tf32.rn.relu (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rn_relu_satfinite,             // llvm.nvvm.f2tf32.rn.relu.satfinite (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rn_satfinite,                  // llvm.nvvm.f2tf32.rn.satfinite (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rna,                           // llvm.nvvm.f2tf32.rna (IntrinsicsNVVM.td:1736)
    nvvm_f2tf32_rna_satfinite,                 // llvm.nvvm.f2tf32.rna.satfinite (IntrinsicsNVVM.td:1736)
    nvvm_f2tf32_rz,                            // llvm.nvvm.f2tf32.rz (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rz_relu,                       // llvm.nvvm.f2tf32.rz.relu (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rz_relu_satfinite,             // llvm.nvvm.f2tf32.rz.relu.satfinite (IntrinsicsNVVM.td:1741)
    nvvm_f2tf32_rz_satfinite,                  // llvm.nvvm.f2tf32.rz.satfinite (IntrinsicsNVVM.td:1741)
    nvvm_f2ui_rm,                              // llvm.nvvm.f2ui.rm (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rm_ftz,                          // llvm.nvvm.f2ui.rm.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rn,                              // llvm.nvvm.f2ui.rn (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rn_ftz,                          // llvm.nvvm.f2ui.rn.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rp,                              // llvm.nvvm.f2ui.rp (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rp_ftz,                          // llvm.nvvm.f2ui.rp.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rz,                              // llvm.nvvm.f2ui.rz (IntrinsicsNVVM.td:1675)
    nvvm_f2ui_rz_ftz,                          // llvm.nvvm.f2ui.rz.ftz (IntrinsicsNVVM.td:1675)
    nvvm_f2ull_rm,                             // llvm.nvvm.f2ull.rm (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rm_ftz,                         // llvm.nvvm.f2ull.rm.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rn,                             // llvm.nvvm.f2ull.rn (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rn_ftz,                         // llvm.nvvm.f2ull.rn.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rp,                             // llvm.nvvm.f2ull.rp (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rp_ftz,                         // llvm.nvvm.f2ull.rp.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rz,                             // llvm.nvvm.f2ull.rz (IntrinsicsNVVM.td:1682)
    nvvm_f2ull_rz_ftz,                         // llvm.nvvm.f2ull.rz.ftz (IntrinsicsNVVM.td:1682)
    nvvm_f32x4_to_e2m1x4_rs_relu_satfinite,    // llvm.nvvm.f32x4.to.e2m1x4.rs.relu.satfinite (IntrinsicsNVVM.td:1779)
    nvvm_f32x4_to_e2m1x4_rs_satfinite,         // llvm.nvvm.f32x4.to.e2m1x4.rs.satfinite (IntrinsicsNVVM.td:1779)
    nvvm_f32x4_to_e2m3x4_rs_relu_satfinite,    // llvm.nvvm.f32x4.to.e2m3x4.rs.relu.satfinite (IntrinsicsNVVM.td:1798)
    nvvm_f32x4_to_e2m3x4_rs_satfinite,         // llvm.nvvm.f32x4.to.e2m3x4.rs.satfinite (IntrinsicsNVVM.td:1798)
    nvvm_f32x4_to_e3m2x4_rs_relu_satfinite,    // llvm.nvvm.f32x4.to.e3m2x4.rs.relu.satfinite (IntrinsicsNVVM.td:1798)
    nvvm_f32x4_to_e3m2x4_rs_satfinite,         // llvm.nvvm.f32x4.to.e3m2x4.rs.satfinite (IntrinsicsNVVM.td:1798)
    nvvm_f32x4_to_e4m3x4_rs_relu_satfinite,    // llvm.nvvm.f32x4.to.e4m3x4.rs.relu.satfinite (IntrinsicsNVVM.td:1762)
    nvvm_f32x4_to_e4m3x4_rs_satfinite,         // llvm.nvvm.f32x4.to.e4m3x4.rs.satfinite (IntrinsicsNVVM.td:1762)
    nvvm_f32x4_to_e5m2x4_rs_relu_satfinite,    // llvm.nvvm.f32x4.to.e5m2x4.rs.relu.satfinite (IntrinsicsNVVM.td:1762)
    nvvm_f32x4_to_e5m2x4_rs_satfinite,         // llvm.nvvm.f32x4.to.e5m2x4.rs.satfinite (IntrinsicsNVVM.td:1762)
    nvvm_fabs,                                 // llvm.nvvm.fabs (IntrinsicsNVVM.td:1425)
    nvvm_fabs_ftz,                             // llvm.nvvm.fabs.ftz (IntrinsicsNVVM.td:1425)
    nvvm_fence_acquire_sync_restrict_space_cluster_scope_cluster,  // llvm.nvvm.fence.acquire.sync_restrict.space.cluster.scope.cluster (IntrinsicsNVVM.td:1912)
    nvvm_fence_mbarrier_init_release_cluster,  // llvm.nvvm.fence.mbarrier_init.release.cluster (IntrinsicsNVVM.td:1908)
    nvvm_fence_proxy_alias,                    // llvm.nvvm.fence.proxy.alias (IntrinsicsNVVM.td:1953)
    nvvm_fence_proxy_async,                    // llvm.nvvm.fence.proxy.async (IntrinsicsNVVM.td:1953)
    nvvm_fence_proxy_async_global,             // llvm.nvvm.fence.proxy.async.global (IntrinsicsNVVM.td:1953)
    nvvm_fence_proxy_async_shared_cluster,     // llvm.nvvm.fence.proxy.async.shared_cluster (IntrinsicsNVVM.td:1953)
    nvvm_fence_proxy_async_shared_cta,         // llvm.nvvm.fence.proxy.async.shared_cta (IntrinsicsNVVM.td:1953)
    nvvm_fence_proxy_async_generic_acquire_sync_restrict_space_cluster_scope_cluster,  // llvm.nvvm.fence.proxy.async_generic.acquire.sync_restrict.space.cluster.scope.cluster (IntrinsicsNVVM.td:1924)
    nvvm_fence_proxy_async_generic_release_sync_restrict_space_cta_scope_cluster,  // llvm.nvvm.fence.proxy.async_generic.release.sync_restrict.space.cta.scope.cluster (IntrinsicsNVVM.td:1928)
    nvvm_fence_proxy_tensormap_generic_acquire_cluster,  // llvm.nvvm.fence.proxy.tensormap_generic.acquire.cluster (IntrinsicsNVVM.td:1939)
    nvvm_fence_proxy_tensormap_generic_acquire_cta,  // llvm.nvvm.fence.proxy.tensormap_generic.acquire.cta (IntrinsicsNVVM.td:1939)
    nvvm_fence_proxy_tensormap_generic_acquire_gpu,  // llvm.nvvm.fence.proxy.tensormap_generic.acquire.gpu (IntrinsicsNVVM.td:1939)
    nvvm_fence_proxy_tensormap_generic_acquire_sys,  // llvm.nvvm.fence.proxy.tensormap_generic.acquire.sys (IntrinsicsNVVM.td:1939)
    nvvm_fence_proxy_tensormap_generic_release_cluster,  // llvm.nvvm.fence.proxy.tensormap_generic.release.cluster (IntrinsicsNVVM.td:1934)
    nvvm_fence_proxy_tensormap_generic_release_cta,  // llvm.nvvm.fence.proxy.tensormap_generic.release.cta (IntrinsicsNVVM.td:1934)
    nvvm_fence_proxy_tensormap_generic_release_gpu,  // llvm.nvvm.fence.proxy.tensormap_generic.release.gpu (IntrinsicsNVVM.td:1934)
    nvvm_fence_proxy_tensormap_generic_release_sys,  // llvm.nvvm.fence.proxy.tensormap_generic.release.sys (IntrinsicsNVVM.td:1934)
    nvvm_fence_release_sync_restrict_space_cta_scope_cluster,  // llvm.nvvm.fence.release.sync_restrict.space.cta.scope.cluster (IntrinsicsNVVM.td:1916)
    nvvm_fence_sc_cluster,                     // llvm.nvvm.fence.sc.cluster (IntrinsicsNVVM.td:1905)
    nvvm_ff_to_e2m1x2_rn_relu_satfinite,       // llvm.nvvm.ff.to.e2m1x2.rn.relu.satfinite (IntrinsicsNVVM.td:1769)
    nvvm_ff_to_e2m1x2_rn_satfinite,            // llvm.nvvm.ff.to.e2m1x2.rn.satfinite (IntrinsicsNVVM.td:1769)
    nvvm_ff_to_e2m3x2_rn_relu_satfinite,       // llvm.nvvm.ff.to.e2m3x2.rn.relu.satfinite (IntrinsicsNVVM.td:1786)
    nvvm_ff_to_e2m3x2_rn_satfinite,            // llvm.nvvm.ff.to.e2m3x2.rn.satfinite (IntrinsicsNVVM.td:1786)
    nvvm_ff_to_e3m2x2_rn_relu_satfinite,       // llvm.nvvm.ff.to.e3m2x2.rn.relu.satfinite (IntrinsicsNVVM.td:1786)
    nvvm_ff_to_e3m2x2_rn_satfinite,            // llvm.nvvm.ff.to.e3m2x2.rn.satfinite (IntrinsicsNVVM.td:1786)
    nvvm_ff_to_e4m3x2_rn,                      // llvm.nvvm.ff.to.e4m3x2.rn (IntrinsicsNVVM.td:1747)
    nvvm_ff_to_e4m3x2_rn_relu,                 // llvm.nvvm.ff.to.e4m3x2.rn.relu (IntrinsicsNVVM.td:1747)
    nvvm_ff_to_e5m2x2_rn,                      // llvm.nvvm.ff.to.e5m2x2.rn (IntrinsicsNVVM.td:1747)
    nvvm_ff_to_e5m2x2_rn_relu,                 // llvm.nvvm.ff.to.e5m2x2.rn.relu (IntrinsicsNVVM.td:1747)
    nvvm_ff_to_ue8m0x2_rp,                     // llvm.nvvm.ff.to.ue8m0x2.rp (IntrinsicsNVVM.td:1807)
    nvvm_ff_to_ue8m0x2_rp_satfinite,           // llvm.nvvm.ff.to.ue8m0x2.rp.satfinite (IntrinsicsNVVM.td:1807)
    nvvm_ff_to_ue8m0x2_rz,                     // llvm.nvvm.ff.to.ue8m0x2.rz (IntrinsicsNVVM.td:1807)
    nvvm_ff_to_ue8m0x2_rz_satfinite,           // llvm.nvvm.ff.to.ue8m0x2.rz.satfinite (IntrinsicsNVVM.td:1807)
    nvvm_ff2bf16x2_rn,                         // llvm.nvvm.ff2bf16x2.rn (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rn_relu,                    // llvm.nvvm.ff2bf16x2.rn.relu (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rn_relu_satfinite,          // llvm.nvvm.ff2bf16x2.rn.relu.satfinite (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rn_satfinite,               // llvm.nvvm.ff2bf16x2.rn.satfinite (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rs,                         // llvm.nvvm.ff2bf16x2.rs (IntrinsicsNVVM.td:1730)
    nvvm_ff2bf16x2_rs_relu,                    // llvm.nvvm.ff2bf16x2.rs.relu (IntrinsicsNVVM.td:1730)
    nvvm_ff2bf16x2_rs_relu_satfinite,          // llvm.nvvm.ff2bf16x2.rs.relu.satfinite (IntrinsicsNVVM.td:1730)
    nvvm_ff2bf16x2_rs_satfinite,               // llvm.nvvm.ff2bf16x2.rs.satfinite (IntrinsicsNVVM.td:1730)
    nvvm_ff2bf16x2_rz,                         // llvm.nvvm.ff2bf16x2.rz (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rz_relu,                    // llvm.nvvm.ff2bf16x2.rz.relu (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rz_relu_satfinite,          // llvm.nvvm.ff2bf16x2.rz.relu.satfinite (IntrinsicsNVVM.td:1708)
    nvvm_ff2bf16x2_rz_satfinite,               // llvm.nvvm.ff2bf16x2.rz.satfinite (IntrinsicsNVVM.td:1708)
    nvvm_ff2f16x2_rn,                          // llvm.nvvm.ff2f16x2.rn (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rn_relu,                     // llvm.nvvm.ff2f16x2.rn.relu (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rn_relu_satfinite,           // llvm.nvvm.ff2f16x2.rn.relu.satfinite (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rn_satfinite,                // llvm.nvvm.ff2f16x2.rn.satfinite (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rs,                          // llvm.nvvm.ff2f16x2.rs (IntrinsicsNVVM.td:1727)
    nvvm_ff2f16x2_rs_relu,                     // llvm.nvvm.ff2f16x2.rs.relu (IntrinsicsNVVM.td:1727)
    nvvm_ff2f16x2_rs_relu_satfinite,           // llvm.nvvm.ff2f16x2.rs.relu.satfinite (IntrinsicsNVVM.td:1727)
    nvvm_ff2f16x2_rs_satfinite,                // llvm.nvvm.ff2f16x2.rs.satfinite (IntrinsicsNVVM.td:1727)
    nvvm_ff2f16x2_rz,                          // llvm.nvvm.ff2f16x2.rz (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rz_relu,                     // llvm.nvvm.ff2f16x2.rz.relu (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rz_relu_satfinite,           // llvm.nvvm.ff2f16x2.rz.relu.satfinite (IntrinsicsNVVM.td:1711)
    nvvm_ff2f16x2_rz_satfinite,                // llvm.nvvm.ff2f16x2.rz.satfinite (IntrinsicsNVVM.td:1711)
    nvvm_flo_s,                                // llvm.nvvm.flo.s (IntrinsicsNVVM.td:1621)
    nvvm_flo_u,                                // llvm.nvvm.flo.u (IntrinsicsNVVM.td:1621)
    nvvm_floor_d,                              // llvm.nvvm.floor.d (IntrinsicsNVVM.td:1417)
    nvvm_floor_f,                              // llvm.nvvm.floor.f (IntrinsicsNVVM.td:1415)
    nvvm_floor_ftz_f,                          // llvm.nvvm.floor.ftz.f (IntrinsicsNVVM.td:1415)
    nvvm_fma_rm_d,                             // llvm.nvvm.fma.rm.d (IntrinsicsNVVM.td:1521)
    nvvm_fma_rm_f,                             // llvm.nvvm.fma.rm.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rm_ftz_f,                         // llvm.nvvm.fma.rm.ftz.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rm_ftz_sat_f,                     // llvm.nvvm.fma.rm.ftz.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rm_sat_f,                         // llvm.nvvm.fma.rm.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rn_bf16,                          // llvm.nvvm.fma.rn.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_bf16x2,                        // llvm.nvvm.fma.rn.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_d,                             // llvm.nvvm.fma.rn.d (IntrinsicsNVVM.td:1521)
    nvvm_fma_rn_f,                             // llvm.nvvm.fma.rn.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rn_f16,                           // llvm.nvvm.fma.rn.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_f16x2,                         // llvm.nvvm.fma.rn.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rn_ftz_bf16,                      // llvm.nvvm.fma.rn.ftz.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_ftz_bf16x2,                    // llvm.nvvm.fma.rn.ftz.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_ftz_f,                         // llvm.nvvm.fma.rn.ftz.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rn_ftz_f16,                       // llvm.nvvm.fma.rn.ftz.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_ftz_f16x2,                     // llvm.nvvm.fma.rn.ftz.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rn_ftz_relu_bf16,                 // llvm.nvvm.fma.rn.ftz.relu.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_ftz_relu_bf16x2,               // llvm.nvvm.fma.rn.ftz.relu.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_ftz_relu_f16,                  // llvm.nvvm.fma.rn.ftz.relu.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_ftz_relu_f16x2,                // llvm.nvvm.fma.rn.ftz.relu.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rn_ftz_sat_bf16,                  // llvm.nvvm.fma.rn.ftz.sat.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_ftz_sat_bf16x2,                // llvm.nvvm.fma.rn.ftz.sat.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_ftz_sat_f,                     // llvm.nvvm.fma.rn.ftz.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rn_ftz_sat_f16,                   // llvm.nvvm.fma.rn.ftz.sat.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_ftz_sat_f16x2,                 // llvm.nvvm.fma.rn.ftz.sat.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rn_relu_bf16,                     // llvm.nvvm.fma.rn.relu.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_relu_bf16x2,                   // llvm.nvvm.fma.rn.relu.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_relu_f16,                      // llvm.nvvm.fma.rn.relu.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_relu_f16x2,                    // llvm.nvvm.fma.rn.relu.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rn_sat_bf16,                      // llvm.nvvm.fma.rn.sat.bf16 (IntrinsicsNVVM.td:1503)
    nvvm_fma_rn_sat_bf16x2,                    // llvm.nvvm.fma.rn.sat.bf16x2 (IntrinsicsNVVM.td:1507)
    nvvm_fma_rn_sat_f,                         // llvm.nvvm.fma.rn.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rn_sat_f16,                       // llvm.nvvm.fma.rn.sat.f16 (IntrinsicsNVVM.td:1495)
    nvvm_fma_rn_sat_f16x2,                     // llvm.nvvm.fma.rn.sat.f16x2 (IntrinsicsNVVM.td:1499)
    nvvm_fma_rp_d,                             // llvm.nvvm.fma.rp.d (IntrinsicsNVVM.td:1521)
    nvvm_fma_rp_f,                             // llvm.nvvm.fma.rp.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rp_ftz_f,                         // llvm.nvvm.fma.rp.ftz.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rp_ftz_sat_f,                     // llvm.nvvm.fma.rp.ftz.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rp_sat_f,                         // llvm.nvvm.fma.rp.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rz_d,                             // llvm.nvvm.fma.rz.d (IntrinsicsNVVM.td:1521)
    nvvm_fma_rz_f,                             // llvm.nvvm.fma.rz.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rz_ftz_f,                         // llvm.nvvm.fma.rz.ftz.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rz_ftz_sat_f,                     // llvm.nvvm.fma.rz.ftz.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fma_rz_sat_f,                         // llvm.nvvm.fma.rz.sat.f (IntrinsicsNVVM.td:1516)
    nvvm_fmax_bf16,                            // llvm.nvvm.fmax.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_bf16x2,                          // llvm.nvvm.fmax.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_d,                               // llvm.nvvm.fmax.d (IntrinsicsNVVM.td:1320)
    nvvm_fmax_f,                               // llvm.nvvm.fmax.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_f16,                             // llvm.nvvm.fmax.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_f16x2,                           // llvm.nvvm.fmax.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_ftz_bf16,                        // llvm.nvvm.fmax.ftz.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_ftz_bf16x2,                      // llvm.nvvm.fmax.ftz.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_ftz_f,                           // llvm.nvvm.fmax.ftz.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_ftz_f16,                         // llvm.nvvm.fmax.ftz.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_ftz_f16x2,                       // llvm.nvvm.fmax.ftz.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_ftz_nan_bf16,                    // llvm.nvvm.fmax.ftz.nan.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_ftz_nan_bf16x2,                  // llvm.nvvm.fmax.ftz.nan.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_ftz_nan_f,                       // llvm.nvvm.fmax.ftz.nan.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_ftz_nan_f16,                     // llvm.nvvm.fmax.ftz.nan.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_ftz_nan_f16x2,                   // llvm.nvvm.fmax.ftz.nan.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_ftz_nan_xorsign_abs_bf16,        // llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_ftz_nan_xorsign_abs_bf16x2,      // llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_ftz_nan_xorsign_abs_f,           // llvm.nvvm.fmax.ftz.nan.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_ftz_nan_xorsign_abs_f16,         // llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_ftz_nan_xorsign_abs_f16x2,       // llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_ftz_xorsign_abs_bf16,            // llvm.nvvm.fmax.ftz.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_ftz_xorsign_abs_bf16x2,          // llvm.nvvm.fmax.ftz.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_ftz_xorsign_abs_f,               // llvm.nvvm.fmax.ftz.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_ftz_xorsign_abs_f16,             // llvm.nvvm.fmax.ftz.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_ftz_xorsign_abs_f16x2,           // llvm.nvvm.fmax.ftz.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_nan_bf16,                        // llvm.nvvm.fmax.nan.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_nan_bf16x2,                      // llvm.nvvm.fmax.nan.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_nan_f,                           // llvm.nvvm.fmax.nan.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_nan_f16,                         // llvm.nvvm.fmax.nan.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_nan_f16x2,                       // llvm.nvvm.fmax.nan.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_nan_xorsign_abs_bf16,            // llvm.nvvm.fmax.nan.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_nan_xorsign_abs_bf16x2,          // llvm.nvvm.fmax.nan.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_nan_xorsign_abs_f,               // llvm.nvvm.fmax.nan.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_nan_xorsign_abs_f16,             // llvm.nvvm.fmax.nan.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_nan_xorsign_abs_f16x2,           // llvm.nvvm.fmax.nan.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmax_xorsign_abs_bf16,                // llvm.nvvm.fmax.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmax_xorsign_abs_bf16x2,              // llvm.nvvm.fmax.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmax_xorsign_abs_f,                   // llvm.nvvm.fmax.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmax_xorsign_abs_f16,                 // llvm.nvvm.fmax.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmax_xorsign_abs_f16x2,               // llvm.nvvm.fmax.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_bf16,                            // llvm.nvvm.fmin.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_bf16x2,                          // llvm.nvvm.fmin.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_d,                               // llvm.nvvm.fmin.d (IntrinsicsNVVM.td:1320)
    nvvm_fmin_f,                               // llvm.nvvm.fmin.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_f16,                             // llvm.nvvm.fmin.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_f16x2,                           // llvm.nvvm.fmin.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_ftz_bf16,                        // llvm.nvvm.fmin.ftz.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_ftz_bf16x2,                      // llvm.nvvm.fmin.ftz.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_ftz_f,                           // llvm.nvvm.fmin.ftz.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_ftz_f16,                         // llvm.nvvm.fmin.ftz.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_ftz_f16x2,                       // llvm.nvvm.fmin.ftz.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_ftz_nan_bf16,                    // llvm.nvvm.fmin.ftz.nan.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_ftz_nan_bf16x2,                  // llvm.nvvm.fmin.ftz.nan.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_ftz_nan_f,                       // llvm.nvvm.fmin.ftz.nan.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_ftz_nan_f16,                     // llvm.nvvm.fmin.ftz.nan.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_ftz_nan_f16x2,                   // llvm.nvvm.fmin.ftz.nan.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_ftz_nan_xorsign_abs_bf16,        // llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_ftz_nan_xorsign_abs_bf16x2,      // llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_ftz_nan_xorsign_abs_f,           // llvm.nvvm.fmin.ftz.nan.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_ftz_nan_xorsign_abs_f16,         // llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_ftz_nan_xorsign_abs_f16x2,       // llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_ftz_xorsign_abs_bf16,            // llvm.nvvm.fmin.ftz.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_ftz_xorsign_abs_bf16x2,          // llvm.nvvm.fmin.ftz.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_ftz_xorsign_abs_f,               // llvm.nvvm.fmin.ftz.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_ftz_xorsign_abs_f16,             // llvm.nvvm.fmin.ftz.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_ftz_xorsign_abs_f16x2,           // llvm.nvvm.fmin.ftz.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_nan_bf16,                        // llvm.nvvm.fmin.nan.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_nan_bf16x2,                      // llvm.nvvm.fmin.nan.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_nan_f,                           // llvm.nvvm.fmin.nan.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_nan_f16,                         // llvm.nvvm.fmin.nan.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_nan_f16x2,                       // llvm.nvvm.fmin.nan.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_nan_xorsign_abs_bf16,            // llvm.nvvm.fmin.nan.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_nan_xorsign_abs_bf16x2,          // llvm.nvvm.fmin.nan.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_nan_xorsign_abs_f,               // llvm.nvvm.fmin.nan.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_nan_xorsign_abs_f16,             // llvm.nvvm.fmin.nan.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_nan_xorsign_abs_f16x2,           // llvm.nvvm.fmin.nan.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fmin_xorsign_abs_bf16,                // llvm.nvvm.fmin.xorsign.abs.bf16 (IntrinsicsNVVM.td:1335)
    nvvm_fmin_xorsign_abs_bf16x2,              // llvm.nvvm.fmin.xorsign.abs.bf16x2 (IntrinsicsNVVM.td:1338)
    nvvm_fmin_xorsign_abs_f,                   // llvm.nvvm.fmin.xorsign.abs.f (IntrinsicsNVVM.td:1326)
    nvvm_fmin_xorsign_abs_f16,                 // llvm.nvvm.fmin.xorsign.abs.f16 (IntrinsicsNVVM.td:1329)
    nvvm_fmin_xorsign_abs_f16x2,               // llvm.nvvm.fmin.xorsign.abs.f16x2 (IntrinsicsNVVM.td:1332)
    nvvm_fns,                                  // llvm.nvvm.fns (IntrinsicsNVVM.td:1643)
    nvvm_fshl_clamp,                           // llvm.nvvm.fshl.clamp (IntrinsicsNVVM.td:1613)
    nvvm_fshr_clamp,                           // llvm.nvvm.fshr.clamp (IntrinsicsNVVM.td:1613)
    nvvm_getctarank,                           // llvm.nvvm.getctarank (IntrinsicsNVVM.td:2760)
    nvvm_getctarank_shared_cluster,            // llvm.nvvm.getctarank.shared.cluster (IntrinsicsNVVM.td:2762)
    nvvm_griddepcontrol_launch_dependents,     // llvm.nvvm.griddepcontrol.launch.dependents (IntrinsicsNVVM.td:3029)
    nvvm_griddepcontrol_wait,                  // llvm.nvvm.griddepcontrol.wait (IntrinsicsNVVM.td:3030)
    nvvm_i2d_rm,                               // llvm.nvvm.i2d.rm (IntrinsicsNVVM.td:1671)
    nvvm_i2d_rn,                               // llvm.nvvm.i2d.rn (IntrinsicsNVVM.td:1671)
    nvvm_i2d_rp,                               // llvm.nvvm.i2d.rp (IntrinsicsNVVM.td:1671)
    nvvm_i2d_rz,                               // llvm.nvvm.i2d.rz (IntrinsicsNVVM.td:1671)
    nvvm_i2f_rm,                               // llvm.nvvm.i2f.rm (IntrinsicsNVVM.td:1678)
    nvvm_i2f_rn,                               // llvm.nvvm.i2f.rn (IntrinsicsNVVM.td:1678)
    nvvm_i2f_rp,                               // llvm.nvvm.i2f.rp (IntrinsicsNVVM.td:1678)
    nvvm_i2f_rz,                               // llvm.nvvm.i2f.rz (IntrinsicsNVVM.td:1678)
    nvvm_idp2a_s_s,                            // llvm.nvvm.idp2a.s.s (IntrinsicsNVVM.td:1602)
    nvvm_idp2a_s_u,                            // llvm.nvvm.idp2a.s.u (IntrinsicsNVVM.td:1602)
    nvvm_idp2a_u_s,                            // llvm.nvvm.idp2a.u.s (IntrinsicsNVVM.td:1602)
    nvvm_idp2a_u_u,                            // llvm.nvvm.idp2a.u.u (IntrinsicsNVVM.td:1602)
    nvvm_idp4a_s_s,                            // llvm.nvvm.idp4a.s.s (IntrinsicsNVVM.td:1599)
    nvvm_idp4a_s_u,                            // llvm.nvvm.idp4a.s.u (IntrinsicsNVVM.td:1599)
    nvvm_idp4a_u_s,                            // llvm.nvvm.idp4a.u.s (IntrinsicsNVVM.td:1599)
    nvvm_idp4a_u_u,                            // llvm.nvvm.idp4a.u.u (IntrinsicsNVVM.td:1599)
    nvvm_internal_addrspace_wrap,              // llvm.nvvm.internal.addrspace.wrap (IntrinsicsNVVM.td:2129)
    nvvm_is_explicit_cluster,                  // llvm.nvvm.is_explicit_cluster (IntrinsicsNVVM.td:2766)
    nvvm_isspacep_const,                       // llvm.nvvm.isspacep.const (IntrinsicsNVVM.td:2158)
    nvvm_isspacep_global,                      // llvm.nvvm.isspacep.global (IntrinsicsNVVM.td:2158)
    nvvm_isspacep_local,                       // llvm.nvvm.isspacep.local (IntrinsicsNVVM.td:2158)
    nvvm_isspacep_shared,                      // llvm.nvvm.isspacep.shared (IntrinsicsNVVM.td:2158)
    nvvm_isspacep_shared_cluster,              // llvm.nvvm.isspacep.shared.cluster (IntrinsicsNVVM.td:2158)
    nvvm_istypep_sampler,                      // llvm.nvvm.istypep.sampler (IntrinsicsNVVM.td:2271)
    nvvm_istypep_surface,                      // llvm.nvvm.istypep.surface (IntrinsicsNVVM.td:2271)
    nvvm_istypep_texture,                      // llvm.nvvm.istypep.texture (IntrinsicsNVVM.td:2271)
    nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8x16_b4x16_p64,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b4x16_p64 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m16n16_x1_trans_b8x16_b6x16_p32,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x1.trans.b8x16.b6x16_p32 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8x16_b4x16_p64,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b4x16_p64 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m16n16_x2_trans_b8x16_b6x16_p32,  // llvm.nvvm.ldmatrix.sync.aligned.m16n16.x2.trans.b8x16.b6x16_p32 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x1_b8x16_b4x16_p64,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b4x16_p64 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x1_b8x16_b6x16_p32,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x1.b8x16.b6x16_p32 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x2_b8x16_b4x16_p64,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b4x16_p64 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x2_b8x16_b6x16_p32,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x2.b8x16.b6x16_p32 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x4_b8x16_b4x16_p64,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b4x16_p64 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n16_x4_b8x16_b6x16_p32,  // llvm.nvvm.ldmatrix.sync.aligned.m8n16.x4.b8x16.b6x16_p32 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x1_b16,    // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x1_trans_b16,  // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x1.trans.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x2_b16,    // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x2_trans_b16,  // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x2.trans.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x4_b16,    // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldmatrix_sync_aligned_m8n8_x4_trans_b16,  // llvm.nvvm.ldmatrix.sync.aligned.m8n8.x4.trans.b16 (IntrinsicsNVVM.td:2727)
    nvvm_ldu_global_f,                         // llvm.nvvm.ldu.global.f (IntrinsicsNVVM.td:2114)
    nvvm_ldu_global_i,                         // llvm.nvvm.ldu.global.i (IntrinsicsNVVM.td:2113)
    nvvm_ldu_global_p,                         // llvm.nvvm.ldu.global.p (IntrinsicsNVVM.td:2115)
    nvvm_lg2_approx_d,                         // llvm.nvvm.lg2.approx.d (IntrinsicsNVVM.td:1478)
    nvvm_lg2_approx_f,                         // llvm.nvvm.lg2.approx.f (IntrinsicsNVVM.td:1475)
    nvvm_lg2_approx_ftz_f,                     // llvm.nvvm.lg2.approx.ftz.f (IntrinsicsNVVM.td:1475)
    nvvm_ll2d_rm,                              // llvm.nvvm.ll2d.rm (IntrinsicsNVVM.td:1691)
    nvvm_ll2d_rn,                              // llvm.nvvm.ll2d.rn (IntrinsicsNVVM.td:1691)
    nvvm_ll2d_rp,                              // llvm.nvvm.ll2d.rp (IntrinsicsNVVM.td:1691)
    nvvm_ll2d_rz,                              // llvm.nvvm.ll2d.rz (IntrinsicsNVVM.td:1691)
    nvvm_ll2f_rm,                              // llvm.nvvm.ll2f.rm (IntrinsicsNVVM.td:1688)
    nvvm_ll2f_rn,                              // llvm.nvvm.ll2f.rn (IntrinsicsNVVM.td:1688)
    nvvm_ll2f_rp,                              // llvm.nvvm.ll2f.rp (IntrinsicsNVVM.td:1688)
    nvvm_ll2f_rz,                              // llvm.nvvm.ll2f.rz (IntrinsicsNVVM.td:1688)
    nvvm_lohi_i2d,                             // llvm.nvvm.lohi.i2d (IntrinsicsNVVM.td:1653)
    nvvm_mapa,                                 // llvm.nvvm.mapa (IntrinsicsNVVM.td:2752)
    nvvm_mapa_shared_cluster,                  // llvm.nvvm.mapa.shared.cluster (IntrinsicsNVVM.td:2754)
    nvvm_match_all_sync_i32p,                  // llvm.nvvm.match.all.sync.i32p (IntrinsicsNVVM.td:2485)
    nvvm_match_all_sync_i64p,                  // llvm.nvvm.match.all.sync.i64p (IntrinsicsNVVM.td:2488)
    nvvm_match_any_sync_i32,                   // llvm.nvvm.match.any.sync.i32 (IntrinsicsNVVM.td:2474)
    nvvm_match_any_sync_i64,                   // llvm.nvvm.match.any.sync.i64 (IntrinsicsNVVM.td:2477)
    nvvm_mbarrier_arrive,                      // llvm.nvvm.mbarrier.arrive (IntrinsicsNVVM.td:2016)
    nvvm_mbarrier_arrive_drop,                 // llvm.nvvm.mbarrier.arrive.drop (IntrinsicsNVVM.td:2025)
    nvvm_mbarrier_arrive_drop_expect_tx_relaxed_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.relaxed.scope.cluster.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_expect_tx_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_expect_tx_relaxed_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.relaxed.scope.cta.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_expect_tx_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_expect_tx_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.scope.cluster.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_expect_tx_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.scope.cluster.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_expect_tx_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.scope.cta.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_expect_tx_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.expect.tx.scope.cta.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_noComplete,      // llvm.nvvm.mbarrier.arrive.drop.noComplete (IntrinsicsNVVM.td:2029)
    nvvm_mbarrier_arrive_drop_noComplete_shared,  // llvm.nvvm.mbarrier.arrive.drop.noComplete.shared (IntrinsicsNVVM.td:2031)
    nvvm_mbarrier_arrive_drop_relaxed_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.relaxed.scope.cluster.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_relaxed_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.relaxed.scope.cta.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_drop_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.scope.cluster.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.scope.cluster.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.drop.scope.cta.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.drop.scope.cta.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_drop_shared,          // llvm.nvvm.mbarrier.arrive.drop.shared (IntrinsicsNVVM.td:2027)
    nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cluster.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cta.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_expect_tx_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.expect.tx.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_expect_tx_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.expect.tx.scope.cluster.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_expect_tx_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.expect.tx.scope.cluster.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_expect_tx_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.expect.tx.scope.cta.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_expect_tx_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.expect.tx.scope.cta.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_noComplete,           // llvm.nvvm.mbarrier.arrive.noComplete (IntrinsicsNVVM.td:2020)
    nvvm_mbarrier_arrive_noComplete_shared,    // llvm.nvvm.mbarrier.arrive.noComplete.shared (IntrinsicsNVVM.td:2022)
    nvvm_mbarrier_arrive_relaxed_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.relaxed.scope.cluster.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_relaxed_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.relaxed.scope.cta.space.cluster (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2077)
    nvvm_mbarrier_arrive_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.arrive.scope.cluster.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.arrive.scope.cluster.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.arrive.scope.cta.space.cluster (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_scope_cta_space_cta,  // llvm.nvvm.mbarrier.arrive.scope.cta.space.cta (IntrinsicsNVVM.td:2074)
    nvvm_mbarrier_arrive_shared,               // llvm.nvvm.mbarrier.arrive.shared (IntrinsicsNVVM.td:2018)
    nvvm_mbarrier_complete_tx_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.complete.tx.scope.cluster.space.cluster (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_complete_tx_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.complete.tx.scope.cluster.space.cta (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_complete_tx_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.complete.tx.scope.cta.space.cluster (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_complete_tx_scope_cta_space_cta,  // llvm.nvvm.mbarrier.complete.tx.scope.cta.space.cta (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_expect_tx_scope_cluster_space_cluster,  // llvm.nvvm.mbarrier.expect.tx.scope.cluster.space.cluster (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_expect_tx_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.expect.tx.scope.cluster.space.cta (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_expect_tx_scope_cta_space_cluster,  // llvm.nvvm.mbarrier.expect.tx.scope.cta.space.cluster (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_expect_tx_scope_cta_space_cta,  // llvm.nvvm.mbarrier.expect.tx.scope.cta.space.cta (IntrinsicsNVVM.td:2051)
    nvvm_mbarrier_init,                        // llvm.nvvm.mbarrier.init (IntrinsicsNVVM.td:2001)
    nvvm_mbarrier_init_shared,                 // llvm.nvvm.mbarrier.init.shared (IntrinsicsNVVM.td:2003)
    nvvm_mbarrier_inval,                       // llvm.nvvm.mbarrier.inval (IntrinsicsNVVM.td:2006)
    nvvm_mbarrier_inval_shared,                // llvm.nvvm.mbarrier.inval.shared (IntrinsicsNVVM.td:2010)
    nvvm_mbarrier_pending_count,               // llvm.nvvm.mbarrier.pending.count (IntrinsicsNVVM.td:2040)
    nvvm_mbarrier_test_wait,                   // llvm.nvvm.mbarrier.test.wait (IntrinsicsNVVM.td:2034)
    nvvm_mbarrier_test_wait_parity_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.test.wait.parity.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_test_wait_parity_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.test.wait.parity.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_test_wait_parity_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.test.wait.parity.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_test_wait_parity_scope_cta_space_cta,  // llvm.nvvm.mbarrier.test.wait.parity.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_test_wait_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.test.wait.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_test_wait_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.test.wait.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_test_wait_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.test.wait.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_test_wait_scope_cta_space_cta,  // llvm.nvvm.mbarrier.test.wait.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_test_wait_shared,            // llvm.nvvm.mbarrier.test.wait.shared (IntrinsicsNVVM.td:2036)
    nvvm_mbarrier_try_wait_parity_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_parity_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_parity_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_parity_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_parity_tl_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.tl.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_parity_tl_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.tl.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_parity_tl_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.tl.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_parity_tl_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.parity.tl.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_tl_relaxed_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.tl.relaxed.scope.cluster.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_tl_relaxed_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.tl.relaxed.scope.cta.space.cta (IntrinsicsNVVM.td:2101)
    nvvm_mbarrier_try_wait_tl_scope_cluster_space_cta,  // llvm.nvvm.mbarrier.try.wait.tl.scope.cluster.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_mbarrier_try_wait_tl_scope_cta_space_cta,  // llvm.nvvm.mbarrier.try.wait.tl.scope.cta.space.cta (IntrinsicsNVVM.td:2098)
    nvvm_membar_cta,                           // llvm.nvvm.membar.cta (IntrinsicsNVVM.td:1902)
    nvvm_membar_gl,                            // llvm.nvvm.membar.gl (IntrinsicsNVVM.td:1903)
    nvvm_membar_sys,                           // llvm.nvvm.membar.sys (IntrinsicsNVVM.td:1904)
    nvvm_mma_and_popc_m16n8k128_row_col_b1,    // llvm.nvvm.mma.and.popc.m16n8k128.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_mma_and_popc_m16n8k256_row_col_b1,    // llvm.nvvm.mma.and.popc.m16n8k256.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_mma_and_popc_m8n8k128_row_col_b1,     // llvm.nvvm.mma.and.popc.m8n8k128.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m1_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m1.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m1_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m1.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m1_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m1.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m1_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m1.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e2m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e2m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e3m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e3m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e3m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e3m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e3m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e3m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e3m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e3m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e3m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e3m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e4m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e4m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e4m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e4m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e4m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e4m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e4m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e4m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e4m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e4m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e5m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e5m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e5m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e5m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e5m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e5m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e5m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e5m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_f32_e5m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.f32.e5m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m1_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m1.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m1_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m1.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m1_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m1.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m1_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m1.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e2m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e2m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e3m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e3m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e3m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e3m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e3m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e3m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e3m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e3m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e3m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e3m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e4m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e4m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e4m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e4m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e4m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e4m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e4m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e4m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e4m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e4m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e5m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e5m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e5m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e5m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e5m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e5m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e5m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e5m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k32_row_col_mxf8f6f4_scale_1x_f32_e5m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k32.row.col.mxf8f6f4.scale.1x.f32.e5m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k64_row_col_mxf4_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k64.row.col.mxf4.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k64_row_col_mxf4_scale_2x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k64.row.col.mxf4.scale.2x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k64_row_col_mxf4nvf4_scale_2x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.block.scale.m16n8k64.row.col.mxf4nvf4.scale.2x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2622)
    nvvm_mma_block_scale_m16n8k64_row_col_mxf4nvf4_scale_4x_f32_e2m1_e2m1_f32_ue4m3,  // llvm.nvvm.mma.block.scale.m16n8k64.row.col.mxf4nvf4.scale.4x.f32.e2m1.e2m1.f32.ue4m3 (IntrinsicsNVVM.td:2622)
    nvvm_mma_m16n8k16_row_col_bf16,            // llvm.nvvm.mma.m16n8k16.row.col.bf16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f16_e4m3_e4m3_f16,  // llvm.nvvm.mma.m16n8k16.row.col.f16.e4m3.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f16_e4m3_e5m2_f16,  // llvm.nvvm.mma.m16n8k16.row.col.f16.e4m3.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f16_e5m2_e4m3_f16,  // llvm.nvvm.mma.m16n8k16.row.col.f16.e5m2.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f16_e5m2_e5m2_f16,  // llvm.nvvm.mma.m16n8k16.row.col.f16.e5m2.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f16_f16,         // llvm.nvvm.mma.m16n8k16.row.col.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.m16n8k16.row.col.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.m16n8k16.row.col.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.m16n8k16.row.col.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.m16n8k16.row.col.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f32_f32,         // llvm.nvvm.mma.m16n8k16.row.col.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_f64,             // llvm.nvvm.mma.m16n8k16.row.col.f64 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_s8,              // llvm.nvvm.mma.m16n8k16.row.col.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_s8_u8,           // llvm.nvvm.mma.m16n8k16.row.col.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_satfinite_s8,    // llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.m16n8k16.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_satfinite_u8,    // llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.m16n8k16.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_u8,              // llvm.nvvm.mma.m16n8k16.row.col.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k16_row_col_u8_s8,           // llvm.nvvm.mma.m16n8k16.row.col.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f16_e4m3_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.f16.e4m3.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f16_e4m3_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.f16.e4m3.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f16_e5m2_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.f16.e5m2.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f16_e5m2_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.f16.e5m2.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m1_e2m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m1.e2m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m1_e3m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m1.e3m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m1_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m1.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m1_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m1.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.m16n8k32.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_s4,              // llvm.nvvm.mma.m16n8k32.row.col.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_s4_u4,           // llvm.nvvm.mma.m16n8k32.row.col.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_s8,              // llvm.nvvm.mma.m16n8k32.row.col.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_s8_u8,           // llvm.nvvm.mma.m16n8k32.row.col.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_s4,    // llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.m16n8k32.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_s8,    // llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.m16n8k32.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_u4,    // llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.m16n8k32.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_u8,    // llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.m16n8k32.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_u4,              // llvm.nvvm.mma.m16n8k32.row.col.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_u4_s4,           // llvm.nvvm.mma.m16n8k32.row.col.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_u8,              // llvm.nvvm.mma.m16n8k32.row.col.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k32_row_col_u8_s8,           // llvm.nvvm.mma.m16n8k32.row.col.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k4_row_col_f64,              // llvm.nvvm.mma.m16n8k4.row.col.f64 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k4_row_col_tf32,             // llvm.nvvm.mma.m16n8k4.row.col.tf32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_s4,              // llvm.nvvm.mma.m16n8k64.row.col.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_s4_u4,           // llvm.nvvm.mma.m16n8k64.row.col.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_satfinite_s4,    // llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.m16n8k64.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_satfinite_u4,    // llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.m16n8k64.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_u4,              // llvm.nvvm.mma.m16n8k64.row.col.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k64_row_col_u4_s4,           // llvm.nvvm.mma.m16n8k64.row.col.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k8_row_col_bf16,             // llvm.nvvm.mma.m16n8k8.row.col.bf16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k8_row_col_f16_f16,          // llvm.nvvm.mma.m16n8k8.row.col.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k8_row_col_f32_f32,          // llvm.nvvm.mma.m16n8k8.row.col.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k8_row_col_f64,              // llvm.nvvm.mma.m16n8k8.row.col.f64 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m16n8k8_row_col_tf32,             // llvm.nvvm.mma.m16n8k8.row.col.tf32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_s8,               // llvm.nvvm.mma.m8n8k16.row.col.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_s8_u8,            // llvm.nvvm.mma.m8n8k16.row.col.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_satfinite_s8,     // llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.m8n8k16.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_satfinite_u8,     // llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.m8n8k16.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_u8,               // llvm.nvvm.mma.m8n8k16.row.col.u8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k16_row_col_u8_s8,            // llvm.nvvm.mma.m8n8k16.row.col.u8.s8 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_s4,               // llvm.nvvm.mma.m8n8k32.row.col.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_s4_u4,            // llvm.nvvm.mma.m8n8k32.row.col.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_satfinite_s4,     // llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.m8n8k32.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_satfinite_u4,     // llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.m8n8k32.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_u4,               // llvm.nvvm.mma.m8n8k32.row.col.u4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k32_row_col_u4_s4,            // llvm.nvvm.mma.m8n8k32.row.col.u4.s4 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_col_f16_f16,           // llvm.nvvm.mma.m8n8k4.col.col.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_col_f32_f16,           // llvm.nvvm.mma.m8n8k4.col.col.f32.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_col_f32_f32,           // llvm.nvvm.mma.m8n8k4.col.col.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_row_f16_f16,           // llvm.nvvm.mma.m8n8k4.col.row.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_row_f32_f16,           // llvm.nvvm.mma.m8n8k4.col.row.f32.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_col_row_f32_f32,           // llvm.nvvm.mma.m8n8k4.col.row.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_col_f16_f16,           // llvm.nvvm.mma.m8n8k4.row.col.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_col_f32_f16,           // llvm.nvvm.mma.m8n8k4.row.col.f32.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_col_f32_f32,           // llvm.nvvm.mma.m8n8k4.row.col.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_col_f64,               // llvm.nvvm.mma.m8n8k4.row.col.f64 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_row_f16_f16,           // llvm.nvvm.mma.m8n8k4.row.row.f16.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_row_f32_f16,           // llvm.nvvm.mma.m8n8k4.row.row.f32.f16 (IntrinsicsNVVM.td:2596)
    nvvm_mma_m8n8k4_row_row_f32_f32,           // llvm.nvvm.mma.m8n8k4.row.row.f32.f32 (IntrinsicsNVVM.td:2596)
    nvvm_mma_sp_m16n8k128_row_col_s4,          // llvm.nvvm.mma.sp.m16n8k128.row.col.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_s4_u4,       // llvm.nvvm.mma.sp.m16n8k128.row.col.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_satfinite_s4,  // llvm.nvvm.mma.sp.m16n8k128.row.col.satfinite.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.sp.m16n8k128.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_satfinite_u4,  // llvm.nvvm.mma.sp.m16n8k128.row.col.satfinite.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.sp.m16n8k128.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_u4,          // llvm.nvvm.mma.sp.m16n8k128.row.col.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k128_row_col_u4_s4,       // llvm.nvvm.mma.sp.m16n8k128.row.col.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k16_row_col_bf16,         // llvm.nvvm.mma.sp.m16n8k16.row.col.bf16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k16_row_col_f16_f16,      // llvm.nvvm.mma.sp.m16n8k16.row.col.f16.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k16_row_col_f32_f32,      // llvm.nvvm.mma.sp.m16n8k16.row.col.f32.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k16_row_col_tf32,         // llvm.nvvm.mma.sp.m16n8k16.row.col.tf32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_bf16,         // llvm.nvvm.mma.sp.m16n8k32.row.col.bf16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_f16_f16,      // llvm.nvvm.mma.sp.m16n8k32.row.col.f16.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_f32_f32,      // llvm.nvvm.mma.sp.m16n8k32.row.col.f32.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_s8,           // llvm.nvvm.mma.sp.m16n8k32.row.col.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_s8_u8,        // llvm.nvvm.mma.sp.m16n8k32.row.col.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_satfinite_s8,  // llvm.nvvm.mma.sp.m16n8k32.row.col.satfinite.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.sp.m16n8k32.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_satfinite_u8,  // llvm.nvvm.mma.sp.m16n8k32.row.col.satfinite.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.sp.m16n8k32.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_u8,           // llvm.nvvm.mma.sp.m16n8k32.row.col.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k32_row_col_u8_s8,        // llvm.nvvm.mma.sp.m16n8k32.row.col.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.sp.m16n8k64.row.col.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.sp.m16n8k64.row.col.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.sp.m16n8k64.row.col.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.sp.m16n8k64.row.col.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_s4,           // llvm.nvvm.mma.sp.m16n8k64.row.col.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_s4_u4,        // llvm.nvvm.mma.sp.m16n8k64.row.col.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_s8,           // llvm.nvvm.mma.sp.m16n8k64.row.col.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_s8_u8,        // llvm.nvvm.mma.sp.m16n8k64.row.col.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_s4,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_s8,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_u4,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_u8,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.sp.m16n8k64.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_u4,           // llvm.nvvm.mma.sp.m16n8k64.row.col.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_u4_s4,        // llvm.nvvm.mma.sp.m16n8k64.row.col.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_u8,           // llvm.nvvm.mma.sp.m16n8k64.row.col.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k64_row_col_u8_s8,        // llvm.nvvm.mma.sp.m16n8k64.row.col.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_m16n8k8_row_col_tf32,          // llvm.nvvm.mma.sp.m16n8k8.row.col.tf32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k128_row_col_mxf4_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k128.row.col.mxf4.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k128_row_col_mxf4_scale_2x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k128.row.col.mxf4.scale.2x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k128_row_col_mxf4nvf4_scale_2x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k128.row.col.mxf4nvf4.scale.2x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k128_row_col_mxf4nvf4_scale_4x_f32_e2m1_e2m1_f32_ue4m3,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k128.row.col.mxf4nvf4.scale.4x.f32.e2m1.e2m1.f32.ue4m3 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m1_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m1.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m1_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m1.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m1_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m1.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m1_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m1.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e2m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e2m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e3m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e3m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e3m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e3m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e3m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e3m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e3m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e3m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e3m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e3m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e4m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e4m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e4m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e4m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e4m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e4m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e4m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e4m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e4m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e4m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e5m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e5m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e5m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e5m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e5m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e5m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e5m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e5m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_f32_e5m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.f32.e5m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m1_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m1.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m1_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m1.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m1_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m1.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m1_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m1.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m1_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m1.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e2m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e2m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e3m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e3m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e3m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e3m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e3m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e3m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e3m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e3m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e3m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e3m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e4m3_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e4m3.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e4m3_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e4m3.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e4m3_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e4m3.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e4m3_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e4m3.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e4m3_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e4m3.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e5m2_e2m1_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e5m2.e2m1.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e5m2_e2m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e5m2.e2m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e5m2_e3m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e5m2.e3m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e5m2_e4m3_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e5m2.e4m3.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_block_scale_m16n8k64_row_col_mxf8f6f4_scale_1x_f32_e5m2_e5m2_f32_ue8m0,  // llvm.nvvm.mma.sp.ordered.metadata.block.scale.m16n8k64.row.col.mxf8f6f4.scale.1x.f32.e5m2.e5m2.f32.ue8m0 (IntrinsicsNVVM.td:2708)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_s4_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_u4_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e3m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e3m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e4m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e4m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e5m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e5m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4_s4,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4.s4 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8 (IntrinsicsNVVM.td:2669)
    nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32,  // llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32 (IntrinsicsNVVM.td:2669)
    nvvm_mma_xor_popc_m16n8k128_row_col_b1,    // llvm.nvvm.mma.xor.popc.m16n8k128.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_mma_xor_popc_m16n8k256_row_col_b1,    // llvm.nvvm.mma.xor.popc.m16n8k256.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_mma_xor_popc_m8n8k128_row_col_b1,     // llvm.nvvm.mma.xor.popc.m8n8k128.row.col.b1 (IntrinsicsNVVM.td:2596)
    nvvm_move_double,                          // llvm.nvvm.move.double (IntrinsicsNVVM.td:2140)
    nvvm_move_float,                           // llvm.nvvm.move.float (IntrinsicsNVVM.td:2139)
    nvvm_move_i16,                             // llvm.nvvm.move.i16 (IntrinsicsNVVM.td:2136)
    nvvm_move_i32,                             // llvm.nvvm.move.i32 (IntrinsicsNVVM.td:2137)
    nvvm_move_i64,                             // llvm.nvvm.move.i64 (IntrinsicsNVVM.td:2138)
    nvvm_move_ptr,                             // llvm.nvvm.move.ptr (IntrinsicsNVVM.td:2141)
    nvvm_mul_rm_d,                             // llvm.nvvm.mul.rm.d (IntrinsicsNVVM.td:1369)
    nvvm_mul_rm_f,                             // llvm.nvvm.mul.rm.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rm_ftz_f,                         // llvm.nvvm.mul.rm.ftz.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rn_d,                             // llvm.nvvm.mul.rn.d (IntrinsicsNVVM.td:1369)
    nvvm_mul_rn_f,                             // llvm.nvvm.mul.rn.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rn_ftz_f,                         // llvm.nvvm.mul.rn.ftz.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rp_d,                             // llvm.nvvm.mul.rp.d (IntrinsicsNVVM.td:1369)
    nvvm_mul_rp_f,                             // llvm.nvvm.mul.rp.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rp_ftz_f,                         // llvm.nvvm.mul.rp.ftz.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rz_d,                             // llvm.nvvm.mul.rz.d (IntrinsicsNVVM.td:1369)
    nvvm_mul_rz_f,                             // llvm.nvvm.mul.rz.f (IntrinsicsNVVM.td:1366)
    nvvm_mul_rz_ftz_f,                         // llvm.nvvm.mul.rz.ftz.f (IntrinsicsNVVM.td:1366)
    nvvm_mul24_i,                              // llvm.nvvm.mul24.i (IntrinsicsNVVM.td:1360)
    nvvm_mul24_ui,                             // llvm.nvvm.mul24.ui (IntrinsicsNVVM.td:1360)
    nvvm_mulhi_i,                              // llvm.nvvm.mulhi.i (IntrinsicsNVVM.td:1354)
    nvvm_mulhi_ll,                             // llvm.nvvm.mulhi.ll (IntrinsicsNVVM.td:1357)
    nvvm_mulhi_s,                              // llvm.nvvm.mulhi.s (IntrinsicsNVVM.td:1351)
    nvvm_mulhi_ui,                             // llvm.nvvm.mulhi.ui (IntrinsicsNVVM.td:1354)
    nvvm_mulhi_ull,                            // llvm.nvvm.mulhi.ull (IntrinsicsNVVM.td:1357)
    nvvm_mulhi_us,                             // llvm.nvvm.mulhi.us (IntrinsicsNVVM.td:1351)
    nvvm_nanosleep,                            // llvm.nvvm.nanosleep (IntrinsicsNVVM.td:1304)
    nvvm_neg_bf16,                             // llvm.nvvm.neg.bf16 (IntrinsicsNVVM.td:1431)
    nvvm_neg_bf16x2,                           // llvm.nvvm.neg.bf16x2 (IntrinsicsNVVM.td:1433)
    nvvm_pm_event_mask,                        // llvm.nvvm.pm.event.mask (IntrinsicsNVVM.td:1311)
    nvvm_prefetch_L1,                          // llvm.nvvm.prefetch.L1 (IntrinsicsNVVM.td:2929)
    nvvm_prefetch_L2,                          // llvm.nvvm.prefetch.L2 (IntrinsicsNVVM.td:2929)
    nvvm_prefetch_global_L1,                   // llvm.nvvm.prefetch.global.L1 (IntrinsicsNVVM.td:2930)
    nvvm_prefetch_global_L2,                   // llvm.nvvm.prefetch.global.L2 (IntrinsicsNVVM.td:2930)
    nvvm_prefetch_global_L2_evict_last,        // llvm.nvvm.prefetch.global.L2.evict.last (IntrinsicsNVVM.td:2937)
    nvvm_prefetch_global_L2_evict_normal,      // llvm.nvvm.prefetch.global.L2.evict.normal (IntrinsicsNVVM.td:2937)
    nvvm_prefetch_local_L1,                    // llvm.nvvm.prefetch.local.L1 (IntrinsicsNVVM.td:2931)
    nvvm_prefetch_local_L2,                    // llvm.nvvm.prefetch.local.L2 (IntrinsicsNVVM.td:2931)
    nvvm_prefetch_tensormap,                   // llvm.nvvm.prefetch.tensormap (IntrinsicsNVVM.td:2934)
    nvvm_prefetchu_L1,                         // llvm.nvvm.prefetchu.L1 (IntrinsicsNVVM.td:2939)
    nvvm_prmt,                                 // llvm.nvvm.prmt (IntrinsicsNVVM.td:1287)
    nvvm_prmt_b4e,                             // llvm.nvvm.prmt.b4e (IntrinsicsNVVM.td:1291)
    nvvm_prmt_ecl,                             // llvm.nvvm.prmt.ecl (IntrinsicsNVVM.td:1298)
    nvvm_prmt_ecr,                             // llvm.nvvm.prmt.ecr (IntrinsicsNVVM.td:1298)
    nvvm_prmt_f4e,                             // llvm.nvvm.prmt.f4e (IntrinsicsNVVM.td:1291)
    nvvm_prmt_rc16,                            // llvm.nvvm.prmt.rc16 (IntrinsicsNVVM.td:1298)
    nvvm_prmt_rc8,                             // llvm.nvvm.prmt.rc8 (IntrinsicsNVVM.td:1298)
    nvvm_rcp_approx_ftz_d,                     // llvm.nvvm.rcp.approx.ftz.d (IntrinsicsNVVM.td:1541)
    nvvm_rcp_approx_ftz_f,                     // llvm.nvvm.rcp.approx.ftz.f (IntrinsicsNVVM.td:1539)
    nvvm_rcp_rm_d,                             // llvm.nvvm.rcp.rm.d (IntrinsicsNVVM.td:1535)
    nvvm_rcp_rm_f,                             // llvm.nvvm.rcp.rm.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rm_ftz_f,                         // llvm.nvvm.rcp.rm.ftz.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rn_d,                             // llvm.nvvm.rcp.rn.d (IntrinsicsNVVM.td:1535)
    nvvm_rcp_rn_f,                             // llvm.nvvm.rcp.rn.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rn_ftz_f,                         // llvm.nvvm.rcp.rn.ftz.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rp_d,                             // llvm.nvvm.rcp.rp.d (IntrinsicsNVVM.td:1535)
    nvvm_rcp_rp_f,                             // llvm.nvvm.rcp.rp.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rp_ftz_f,                         // llvm.nvvm.rcp.rp.ftz.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rz_d,                             // llvm.nvvm.rcp.rz.d (IntrinsicsNVVM.td:1535)
    nvvm_rcp_rz_f,                             // llvm.nvvm.rcp.rz.f (IntrinsicsNVVM.td:1532)
    nvvm_rcp_rz_ftz_f,                         // llvm.nvvm.rcp.rz.ftz.f (IntrinsicsNVVM.td:1532)
    nvvm_read_ptx_sreg_aggr_smem_size,         // llvm.nvvm.read.ptx.sreg.aggr_smem_size (IntrinsicsNVVM.td:2417)
    nvvm_read_ptx_sreg_clock,                  // llvm.nvvm.read.ptx.sreg.clock (IntrinsicsNVVM.td:2383)
    nvvm_read_ptx_sreg_clock64,                // llvm.nvvm.read.ptx.sreg.clock64 (IntrinsicsNVVM.td:2384)
    nvvm_read_ptx_sreg_cluster_ctaid_w,        // llvm.nvvm.read.ptx.sreg.cluster.ctaid.w (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_ctaid_x,        // llvm.nvvm.read.ptx.sreg.cluster.ctaid.x (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_ctaid_y,        // llvm.nvvm.read.ptx.sreg.cluster.ctaid.y (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_ctaid_z,        // llvm.nvvm.read.ptx.sreg.cluster.ctaid.z (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_ctarank,        // llvm.nvvm.read.ptx.sreg.cluster.ctarank (IntrinsicsNVVM.td:2412)
    nvvm_read_ptx_sreg_cluster_nctaid_w,       // llvm.nvvm.read.ptx.sreg.cluster.nctaid.w (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_nctaid_x,       // llvm.nvvm.read.ptx.sreg.cluster.nctaid.x (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_nctaid_y,       // llvm.nvvm.read.ptx.sreg.cluster.nctaid.y (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_nctaid_z,       // llvm.nvvm.read.ptx.sreg.cluster.nctaid.z (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_cluster_nctarank,       // llvm.nvvm.read.ptx.sreg.cluster.nctarank (IntrinsicsNVVM.td:2413)
    nvvm_read_ptx_sreg_clusterid_w,            // llvm.nvvm.read.ptx.sreg.clusterid.w (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_clusterid_x,            // llvm.nvvm.read.ptx.sreg.clusterid.x (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_clusterid_y,            // llvm.nvvm.read.ptx.sreg.clusterid.y (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_clusterid_z,            // llvm.nvvm.read.ptx.sreg.clusterid.z (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_ctaid_w,                // llvm.nvvm.read.ptx.sreg.ctaid.w (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ctaid_x,                // llvm.nvvm.read.ptx.sreg.ctaid.x (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ctaid_y,                // llvm.nvvm.read.ptx.sreg.ctaid.y (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ctaid_z,                // llvm.nvvm.read.ptx.sreg.ctaid.z (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_dynamic_smem_size,      // llvm.nvvm.read.ptx.sreg.dynamic_smem_size (IntrinsicsNVVM.td:2419)
    nvvm_read_ptx_sreg_envreg0,                // llvm.nvvm.read.ptx.sreg.envreg0 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg1,                // llvm.nvvm.read.ptx.sreg.envreg1 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg10,               // llvm.nvvm.read.ptx.sreg.envreg10 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg11,               // llvm.nvvm.read.ptx.sreg.envreg11 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg12,               // llvm.nvvm.read.ptx.sreg.envreg12 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg13,               // llvm.nvvm.read.ptx.sreg.envreg13 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg14,               // llvm.nvvm.read.ptx.sreg.envreg14 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg15,               // llvm.nvvm.read.ptx.sreg.envreg15 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg16,               // llvm.nvvm.read.ptx.sreg.envreg16 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg17,               // llvm.nvvm.read.ptx.sreg.envreg17 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg18,               // llvm.nvvm.read.ptx.sreg.envreg18 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg19,               // llvm.nvvm.read.ptx.sreg.envreg19 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg2,                // llvm.nvvm.read.ptx.sreg.envreg2 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg20,               // llvm.nvvm.read.ptx.sreg.envreg20 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg21,               // llvm.nvvm.read.ptx.sreg.envreg21 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg22,               // llvm.nvvm.read.ptx.sreg.envreg22 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg23,               // llvm.nvvm.read.ptx.sreg.envreg23 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg24,               // llvm.nvvm.read.ptx.sreg.envreg24 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg25,               // llvm.nvvm.read.ptx.sreg.envreg25 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg26,               // llvm.nvvm.read.ptx.sreg.envreg26 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg27,               // llvm.nvvm.read.ptx.sreg.envreg27 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg28,               // llvm.nvvm.read.ptx.sreg.envreg28 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg29,               // llvm.nvvm.read.ptx.sreg.envreg29 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg3,                // llvm.nvvm.read.ptx.sreg.envreg3 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg30,               // llvm.nvvm.read.ptx.sreg.envreg30 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg31,               // llvm.nvvm.read.ptx.sreg.envreg31 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg4,                // llvm.nvvm.read.ptx.sreg.envreg4 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg5,                // llvm.nvvm.read.ptx.sreg.envreg5 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg6,                // llvm.nvvm.read.ptx.sreg.envreg6 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg7,                // llvm.nvvm.read.ptx.sreg.envreg7 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg8,                // llvm.nvvm.read.ptx.sreg.envreg8 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_envreg9,                // llvm.nvvm.read.ptx.sreg.envreg9 (IntrinsicsNVVM.td:2398)
    nvvm_read_ptx_sreg_globaltimer,            // llvm.nvvm.read.ptx.sreg.globaltimer (IntrinsicsNVVM.td:2386)
    nvvm_read_ptx_sreg_globaltimer_lo,         // llvm.nvvm.read.ptx.sreg.globaltimer.lo (IntrinsicsNVVM.td:2387)
    nvvm_read_ptx_sreg_gridid,                 // llvm.nvvm.read.ptx.sreg.gridid (IntrinsicsNVVM.td:2375)
    nvvm_read_ptx_sreg_laneid,                 // llvm.nvvm.read.ptx.sreg.laneid (IntrinsicsNVVM.td:2364)
    nvvm_read_ptx_sreg_lanemask_eq,            // llvm.nvvm.read.ptx.sreg.lanemask.eq (IntrinsicsNVVM.td:2377)
    nvvm_read_ptx_sreg_lanemask_ge,            // llvm.nvvm.read.ptx.sreg.lanemask.ge (IntrinsicsNVVM.td:2380)
    nvvm_read_ptx_sreg_lanemask_gt,            // llvm.nvvm.read.ptx.sreg.lanemask.gt (IntrinsicsNVVM.td:2381)
    nvvm_read_ptx_sreg_lanemask_le,            // llvm.nvvm.read.ptx.sreg.lanemask.le (IntrinsicsNVVM.td:2378)
    nvvm_read_ptx_sreg_lanemask_lt,            // llvm.nvvm.read.ptx.sreg.lanemask.lt (IntrinsicsNVVM.td:2379)
    nvvm_read_ptx_sreg_nclusterid_w,           // llvm.nvvm.read.ptx.sreg.nclusterid.w (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_nclusterid_x,           // llvm.nvvm.read.ptx.sreg.nclusterid.x (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_nclusterid_y,           // llvm.nvvm.read.ptx.sreg.nclusterid.y (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_nclusterid_z,           // llvm.nvvm.read.ptx.sreg.nclusterid.z (IntrinsicsNVVM.td:2331)
    nvvm_read_ptx_sreg_nctaid_w,               // llvm.nvvm.read.ptx.sreg.nctaid.w (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_nctaid_x,               // llvm.nvvm.read.ptx.sreg.nctaid.x (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_nctaid_y,               // llvm.nvvm.read.ptx.sreg.nctaid.y (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_nctaid_z,               // llvm.nvvm.read.ptx.sreg.nctaid.z (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_nsmid,                  // llvm.nvvm.read.ptx.sreg.nsmid (IntrinsicsNVVM.td:2374)
    nvvm_read_ptx_sreg_ntid_w,                 // llvm.nvvm.read.ptx.sreg.ntid.w (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ntid_x,                 // llvm.nvvm.read.ptx.sreg.ntid.x (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ntid_y,                 // llvm.nvvm.read.ptx.sreg.ntid.y (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_ntid_z,                 // llvm.nvvm.read.ptx.sreg.ntid.z (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_nwarpid,                // llvm.nvvm.read.ptx.sreg.nwarpid (IntrinsicsNVVM.td:2368)
    nvvm_read_ptx_sreg_pm0,                    // llvm.nvvm.read.ptx.sreg.pm0 (IntrinsicsNVVM.td:2389)
    nvvm_read_ptx_sreg_pm1,                    // llvm.nvvm.read.ptx.sreg.pm1 (IntrinsicsNVVM.td:2390)
    nvvm_read_ptx_sreg_pm2,                    // llvm.nvvm.read.ptx.sreg.pm2 (IntrinsicsNVVM.td:2391)
    nvvm_read_ptx_sreg_pm3,                    // llvm.nvvm.read.ptx.sreg.pm3 (IntrinsicsNVVM.td:2392)
    nvvm_read_ptx_sreg_smid,                   // llvm.nvvm.read.ptx.sreg.smid (IntrinsicsNVVM.td:2373)
    nvvm_read_ptx_sreg_tid_w,                  // llvm.nvvm.read.ptx.sreg.tid.w (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_tid_x,                  // llvm.nvvm.read.ptx.sreg.tid.x (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_tid_y,                  // llvm.nvvm.read.ptx.sreg.tid.y (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_tid_z,                  // llvm.nvvm.read.ptx.sreg.tid.z (IntrinsicsNVVM.td:2322)
    nvvm_read_ptx_sreg_total_smem_size,        // llvm.nvvm.read.ptx.sreg.total_smem_size (IntrinsicsNVVM.td:2415)
    nvvm_read_ptx_sreg_warpid,                 // llvm.nvvm.read.ptx.sreg.warpid (IntrinsicsNVVM.td:2367)
    nvvm_read_ptx_sreg_warpsize,               // llvm.nvvm.read.ptx.sreg.warpsize (IntrinsicsNVVM.td:2394)
    nvvm_redux_sync_add,                       // llvm.nvvm.redux.sync.add (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_and,                       // llvm.nvvm.redux.sync.and (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_fmax,                      // llvm.nvvm.redux.sync.fmax (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmax_NaN,                  // llvm.nvvm.redux.sync.fmax.NaN (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmax_abs,                  // llvm.nvvm.redux.sync.fmax.abs (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmax_abs_NaN,              // llvm.nvvm.redux.sync.fmax.abs.NaN (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmin,                      // llvm.nvvm.redux.sync.fmin (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmin_NaN,                  // llvm.nvvm.redux.sync.fmin.NaN (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmin_abs,                  // llvm.nvvm.redux.sync.fmin.abs (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_fmin_abs_NaN,              // llvm.nvvm.redux.sync.fmin.abs.NaN (IntrinsicsNVVM.td:2513)
    nvvm_redux_sync_max,                       // llvm.nvvm.redux.sync.max (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_min,                       // llvm.nvvm.redux.sync.min (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_or,                        // llvm.nvvm.redux.sync.or (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_umax,                      // llvm.nvvm.redux.sync.umax (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_umin,                      // llvm.nvvm.redux.sync.umin (IntrinsicsNVVM.td:2506)
    nvvm_redux_sync_xor,                       // llvm.nvvm.redux.sync.xor (IntrinsicsNVVM.td:2506)
    nvvm_reflect,                              // llvm.nvvm.reflect (IntrinsicsNVVM.td:2154)
    nvvm_round_d,                              // llvm.nvvm.round.d (IntrinsicsNVVM.td:1443)
    nvvm_round_f,                              // llvm.nvvm.round.f (IntrinsicsNVVM.td:1440)
    nvvm_round_ftz_f,                          // llvm.nvvm.round.ftz.f (IntrinsicsNVVM.td:1440)
    nvvm_rsqrt_approx_d,                       // llvm.nvvm.rsqrt.approx.d (IntrinsicsNVVM.td:1573)
    nvvm_rsqrt_approx_f,                       // llvm.nvvm.rsqrt.approx.f (IntrinsicsNVVM.td:1571)
    nvvm_rsqrt_approx_ftz_d,                   // llvm.nvvm.rsqrt.approx.ftz.d (IntrinsicsNVVM.td:1573)
    nvvm_rsqrt_approx_ftz_f,                   // llvm.nvvm.rsqrt.approx.ftz.f (IntrinsicsNVVM.td:1571)
    nvvm_sad_i,                                // llvm.nvvm.sad.i (IntrinsicsNVVM.td:1403)
    nvvm_sad_ll,                               // llvm.nvvm.sad.ll (IntrinsicsNVVM.td:1406)
    nvvm_sad_s,                                // llvm.nvvm.sad.s (IntrinsicsNVVM.td:1400)
    nvvm_sad_ui,                               // llvm.nvvm.sad.ui (IntrinsicsNVVM.td:1403)
    nvvm_sad_ull,                              // llvm.nvvm.sad.ull (IntrinsicsNVVM.td:1406)
    nvvm_sad_us,                               // llvm.nvvm.sad.us (IntrinsicsNVVM.td:1400)
    nvvm_saturate_d,                           // llvm.nvvm.saturate.d (IntrinsicsNVVM.td:1463)
    nvvm_saturate_f,                           // llvm.nvvm.saturate.f (IntrinsicsNVVM.td:1460)
    nvvm_saturate_ftz_f,                       // llvm.nvvm.saturate.ftz.f (IntrinsicsNVVM.td:1460)
    nvvm_setmaxnreg_dec_sync_aligned_u32,      // llvm.nvvm.setmaxnreg.dec.sync.aligned.u32 (IntrinsicsNVVM.td:2773)
    nvvm_setmaxnreg_inc_sync_aligned_u32,      // llvm.nvvm.setmaxnreg.inc.sync.aligned.u32 (IntrinsicsNVVM.td:2773)
    nvvm_sext_clamp,                           // llvm.nvvm.sext.clamp (IntrinsicsNVVM.td:1630)
    nvvm_sext_wrap,                            // llvm.nvvm.sext.wrap (IntrinsicsNVVM.td:1630)
    nvvm_shfl_bfly_f32,                        // llvm.nvvm.shfl.bfly.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_bfly_f32p,                       // llvm.nvvm.shfl.bfly.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_bfly_i32,                        // llvm.nvvm.shfl.bfly.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_bfly_i32p,                       // llvm.nvvm.shfl.bfly.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_down_f32,                        // llvm.nvvm.shfl.down.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_down_f32p,                       // llvm.nvvm.shfl.down.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_down_i32,                        // llvm.nvvm.shfl.down.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_down_i32p,                       // llvm.nvvm.shfl.down.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_idx_f32,                         // llvm.nvvm.shfl.idx.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_idx_f32p,                        // llvm.nvvm.shfl.idx.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_idx_i32,                         // llvm.nvvm.shfl.idx.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_idx_i32p,                        // llvm.nvvm.shfl.idx.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_bfly_f32,                   // llvm.nvvm.shfl.sync.bfly.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_bfly_f32p,                  // llvm.nvvm.shfl.sync.bfly.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_bfly_i32,                   // llvm.nvvm.shfl.sync.bfly.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_bfly_i32p,                  // llvm.nvvm.shfl.sync.bfly.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_down_f32,                   // llvm.nvvm.shfl.sync.down.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_down_f32p,                  // llvm.nvvm.shfl.sync.down.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_down_i32,                   // llvm.nvvm.shfl.sync.down.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_down_i32p,                  // llvm.nvvm.shfl.sync.down.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_idx_f32,                    // llvm.nvvm.shfl.sync.idx.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_idx_f32p,                   // llvm.nvvm.shfl.sync.idx.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_idx_i32,                    // llvm.nvvm.shfl.sync.idx.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_idx_i32p,                   // llvm.nvvm.shfl.sync.idx.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_up_f32,                     // llvm.nvvm.shfl.sync.up.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_up_f32p,                    // llvm.nvvm.shfl.sync.up.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_sync_up_i32,                     // llvm.nvvm.shfl.sync.up.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_sync_up_i32p,                    // llvm.nvvm.shfl.sync.up.i32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_up_f32,                          // llvm.nvvm.shfl.up.f32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_up_f32p,                         // llvm.nvvm.shfl.up.f32p (IntrinsicsNVVM.td:2435)
    nvvm_shfl_up_i32,                          // llvm.nvvm.shfl.up.i32 (IntrinsicsNVVM.td:2433)
    nvvm_shfl_up_i32p,                         // llvm.nvvm.shfl.up.i32p (IntrinsicsNVVM.td:2435)
    nvvm_sin_approx_f,                         // llvm.nvvm.sin.approx.f (IntrinsicsNVVM.td:1487)
    nvvm_sin_approx_ftz_f,                     // llvm.nvvm.sin.approx.ftz.f (IntrinsicsNVVM.td:1487)
    nvvm_sqrt_approx_f,                        // llvm.nvvm.sqrt.approx.f (IntrinsicsNVVM.td:1562)
    nvvm_sqrt_approx_ftz_f,                    // llvm.nvvm.sqrt.approx.ftz.f (IntrinsicsNVVM.td:1562)
    nvvm_sqrt_f,                               // llvm.nvvm.sqrt.f (IntrinsicsNVVM.td:1558)
    nvvm_sqrt_rm_d,                            // llvm.nvvm.sqrt.rm.d (IntrinsicsNVVM.td:1554)
    nvvm_sqrt_rm_f,                            // llvm.nvvm.sqrt.rm.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rm_ftz_f,                        // llvm.nvvm.sqrt.rm.ftz.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rn_d,                            // llvm.nvvm.sqrt.rn.d (IntrinsicsNVVM.td:1554)
    nvvm_sqrt_rn_f,                            // llvm.nvvm.sqrt.rn.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rn_ftz_f,                        // llvm.nvvm.sqrt.rn.ftz.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rp_d,                            // llvm.nvvm.sqrt.rp.d (IntrinsicsNVVM.td:1554)
    nvvm_sqrt_rp_f,                            // llvm.nvvm.sqrt.rp.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rp_ftz_f,                        // llvm.nvvm.sqrt.rp.ftz.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rz_d,                            // llvm.nvvm.sqrt.rz.d (IntrinsicsNVVM.td:1554)
    nvvm_sqrt_rz_f,                            // llvm.nvvm.sqrt.rz.f (IntrinsicsNVVM.td:1551)
    nvvm_sqrt_rz_ftz_f,                        // llvm.nvvm.sqrt.rz.ftz.f (IntrinsicsNVVM.td:1551)
    nvvm_st_bulk,                              // llvm.nvvm.st.bulk (IntrinsicsNVVM.td:3157)
    nvvm_st_bulk_shared_cta,                   // llvm.nvvm.st.bulk.shared.cta (IntrinsicsNVVM.td:3160)
    nvvm_stmatrix_sync_aligned_m16n8_x1_trans_b8,  // llvm.nvvm.stmatrix.sync.aligned.m16n8.x1.trans.b8 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m16n8_x2_trans_b8,  // llvm.nvvm.stmatrix.sync.aligned.m16n8.x2.trans.b8 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m16n8_x4_trans_b8,  // llvm.nvvm.stmatrix.sync.aligned.m16n8.x4.trans.b8 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x1_b16,    // llvm.nvvm.stmatrix.sync.aligned.m8n8.x1.b16 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x1_trans_b16,  // llvm.nvvm.stmatrix.sync.aligned.m8n8.x1.trans.b16 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x2_b16,    // llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.b16 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x2_trans_b16,  // llvm.nvvm.stmatrix.sync.aligned.m8n8.x2.trans.b16 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x4_b16,    // llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.b16 (IntrinsicsNVVM.td:2744)
    nvvm_stmatrix_sync_aligned_m8n8_x4_trans_b16,  // llvm.nvvm.stmatrix.sync.aligned.m8n8.x4.trans.b16 (IntrinsicsNVVM.td:2744)
    nvvm_suld_1d_array_i16_clamp,              // llvm.nvvm.suld.1d.array.i16.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i16_trap,               // llvm.nvvm.suld.1d.array.i16.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i16_zero,               // llvm.nvvm.suld.1d.array.i16.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i32_clamp,              // llvm.nvvm.suld.1d.array.i32.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i32_trap,               // llvm.nvvm.suld.1d.array.i32.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i32_zero,               // llvm.nvvm.suld.1d.array.i32.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i64_clamp,              // llvm.nvvm.suld.1d.array.i64.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i64_trap,               // llvm.nvvm.suld.1d.array.i64.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i64_zero,               // llvm.nvvm.suld.1d.array.i64.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i8_clamp,               // llvm.nvvm.suld.1d.array.i8.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i8_trap,                // llvm.nvvm.suld.1d.array.i8.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_i8_zero,                // llvm.nvvm.suld.1d.array.i8.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i16_clamp,            // llvm.nvvm.suld.1d.array.v2i16.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i16_trap,             // llvm.nvvm.suld.1d.array.v2i16.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i16_zero,             // llvm.nvvm.suld.1d.array.v2i16.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i32_clamp,            // llvm.nvvm.suld.1d.array.v2i32.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i32_trap,             // llvm.nvvm.suld.1d.array.v2i32.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i32_zero,             // llvm.nvvm.suld.1d.array.v2i32.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i64_clamp,            // llvm.nvvm.suld.1d.array.v2i64.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i64_trap,             // llvm.nvvm.suld.1d.array.v2i64.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i64_zero,             // llvm.nvvm.suld.1d.array.v2i64.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i8_clamp,             // llvm.nvvm.suld.1d.array.v2i8.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i8_trap,              // llvm.nvvm.suld.1d.array.v2i8.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v2i8_zero,              // llvm.nvvm.suld.1d.array.v2i8.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i16_clamp,            // llvm.nvvm.suld.1d.array.v4i16.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i16_trap,             // llvm.nvvm.suld.1d.array.v4i16.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i16_zero,             // llvm.nvvm.suld.1d.array.v4i16.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i32_clamp,            // llvm.nvvm.suld.1d.array.v4i32.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i32_trap,             // llvm.nvvm.suld.1d.array.v4i32.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i32_zero,             // llvm.nvvm.suld.1d.array.v4i32.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i8_clamp,             // llvm.nvvm.suld.1d.array.v4i8.clamp (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i8_trap,              // llvm.nvvm.suld.1d.array.v4i8.trap (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_array_v4i8_zero,              // llvm.nvvm.suld.1d.array.v4i8.zero (IntrinsicsNVVM.td:2235)
    nvvm_suld_1d_i16_clamp,                    // llvm.nvvm.suld.1d.i16.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i16_trap,                     // llvm.nvvm.suld.1d.i16.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i16_zero,                     // llvm.nvvm.suld.1d.i16.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i32_clamp,                    // llvm.nvvm.suld.1d.i32.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i32_trap,                     // llvm.nvvm.suld.1d.i32.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i32_zero,                     // llvm.nvvm.suld.1d.i32.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i64_clamp,                    // llvm.nvvm.suld.1d.i64.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i64_trap,                     // llvm.nvvm.suld.1d.i64.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i64_zero,                     // llvm.nvvm.suld.1d.i64.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i8_clamp,                     // llvm.nvvm.suld.1d.i8.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i8_trap,                      // llvm.nvvm.suld.1d.i8.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_i8_zero,                      // llvm.nvvm.suld.1d.i8.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i16_clamp,                  // llvm.nvvm.suld.1d.v2i16.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i16_trap,                   // llvm.nvvm.suld.1d.v2i16.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i16_zero,                   // llvm.nvvm.suld.1d.v2i16.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i32_clamp,                  // llvm.nvvm.suld.1d.v2i32.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i32_trap,                   // llvm.nvvm.suld.1d.v2i32.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i32_zero,                   // llvm.nvvm.suld.1d.v2i32.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i64_clamp,                  // llvm.nvvm.suld.1d.v2i64.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i64_trap,                   // llvm.nvvm.suld.1d.v2i64.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i64_zero,                   // llvm.nvvm.suld.1d.v2i64.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i8_clamp,                   // llvm.nvvm.suld.1d.v2i8.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i8_trap,                    // llvm.nvvm.suld.1d.v2i8.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v2i8_zero,                    // llvm.nvvm.suld.1d.v2i8.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i16_clamp,                  // llvm.nvvm.suld.1d.v4i16.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i16_trap,                   // llvm.nvvm.suld.1d.v4i16.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i16_zero,                   // llvm.nvvm.suld.1d.v4i16.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i32_clamp,                  // llvm.nvvm.suld.1d.v4i32.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i32_trap,                   // llvm.nvvm.suld.1d.v4i32.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i32_zero,                   // llvm.nvvm.suld.1d.v4i32.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i8_clamp,                   // llvm.nvvm.suld.1d.v4i8.clamp (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i8_trap,                    // llvm.nvvm.suld.1d.v4i8.trap (IntrinsicsNVVM.td:2231)
    nvvm_suld_1d_v4i8_zero,                    // llvm.nvvm.suld.1d.v4i8.zero (IntrinsicsNVVM.td:2231)
    nvvm_suld_2d_array_i16_clamp,              // llvm.nvvm.suld.2d.array.i16.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i16_trap,               // llvm.nvvm.suld.2d.array.i16.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i16_zero,               // llvm.nvvm.suld.2d.array.i16.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i32_clamp,              // llvm.nvvm.suld.2d.array.i32.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i32_trap,               // llvm.nvvm.suld.2d.array.i32.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i32_zero,               // llvm.nvvm.suld.2d.array.i32.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i64_clamp,              // llvm.nvvm.suld.2d.array.i64.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i64_trap,               // llvm.nvvm.suld.2d.array.i64.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i64_zero,               // llvm.nvvm.suld.2d.array.i64.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i8_clamp,               // llvm.nvvm.suld.2d.array.i8.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i8_trap,                // llvm.nvvm.suld.2d.array.i8.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_i8_zero,                // llvm.nvvm.suld.2d.array.i8.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i16_clamp,            // llvm.nvvm.suld.2d.array.v2i16.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i16_trap,             // llvm.nvvm.suld.2d.array.v2i16.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i16_zero,             // llvm.nvvm.suld.2d.array.v2i16.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i32_clamp,            // llvm.nvvm.suld.2d.array.v2i32.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i32_trap,             // llvm.nvvm.suld.2d.array.v2i32.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i32_zero,             // llvm.nvvm.suld.2d.array.v2i32.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i64_clamp,            // llvm.nvvm.suld.2d.array.v2i64.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i64_trap,             // llvm.nvvm.suld.2d.array.v2i64.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i64_zero,             // llvm.nvvm.suld.2d.array.v2i64.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i8_clamp,             // llvm.nvvm.suld.2d.array.v2i8.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i8_trap,              // llvm.nvvm.suld.2d.array.v2i8.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v2i8_zero,              // llvm.nvvm.suld.2d.array.v2i8.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i16_clamp,            // llvm.nvvm.suld.2d.array.v4i16.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i16_trap,             // llvm.nvvm.suld.2d.array.v4i16.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i16_zero,             // llvm.nvvm.suld.2d.array.v4i16.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i32_clamp,            // llvm.nvvm.suld.2d.array.v4i32.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i32_trap,             // llvm.nvvm.suld.2d.array.v4i32.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i32_zero,             // llvm.nvvm.suld.2d.array.v4i32.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i8_clamp,             // llvm.nvvm.suld.2d.array.v4i8.clamp (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i8_trap,              // llvm.nvvm.suld.2d.array.v4i8.trap (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_array_v4i8_zero,              // llvm.nvvm.suld.2d.array.v4i8.zero (IntrinsicsNVVM.td:2243)
    nvvm_suld_2d_i16_clamp,                    // llvm.nvvm.suld.2d.i16.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i16_trap,                     // llvm.nvvm.suld.2d.i16.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i16_zero,                     // llvm.nvvm.suld.2d.i16.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i32_clamp,                    // llvm.nvvm.suld.2d.i32.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i32_trap,                     // llvm.nvvm.suld.2d.i32.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i32_zero,                     // llvm.nvvm.suld.2d.i32.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i64_clamp,                    // llvm.nvvm.suld.2d.i64.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i64_trap,                     // llvm.nvvm.suld.2d.i64.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i64_zero,                     // llvm.nvvm.suld.2d.i64.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i8_clamp,                     // llvm.nvvm.suld.2d.i8.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i8_trap,                      // llvm.nvvm.suld.2d.i8.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_i8_zero,                      // llvm.nvvm.suld.2d.i8.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i16_clamp,                  // llvm.nvvm.suld.2d.v2i16.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i16_trap,                   // llvm.nvvm.suld.2d.v2i16.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i16_zero,                   // llvm.nvvm.suld.2d.v2i16.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i32_clamp,                  // llvm.nvvm.suld.2d.v2i32.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i32_trap,                   // llvm.nvvm.suld.2d.v2i32.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i32_zero,                   // llvm.nvvm.suld.2d.v2i32.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i64_clamp,                  // llvm.nvvm.suld.2d.v2i64.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i64_trap,                   // llvm.nvvm.suld.2d.v2i64.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i64_zero,                   // llvm.nvvm.suld.2d.v2i64.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i8_clamp,                   // llvm.nvvm.suld.2d.v2i8.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i8_trap,                    // llvm.nvvm.suld.2d.v2i8.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v2i8_zero,                    // llvm.nvvm.suld.2d.v2i8.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i16_clamp,                  // llvm.nvvm.suld.2d.v4i16.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i16_trap,                   // llvm.nvvm.suld.2d.v4i16.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i16_zero,                   // llvm.nvvm.suld.2d.v4i16.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i32_clamp,                  // llvm.nvvm.suld.2d.v4i32.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i32_trap,                   // llvm.nvvm.suld.2d.v4i32.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i32_zero,                   // llvm.nvvm.suld.2d.v4i32.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i8_clamp,                   // llvm.nvvm.suld.2d.v4i8.clamp (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i8_trap,                    // llvm.nvvm.suld.2d.v4i8.trap (IntrinsicsNVVM.td:2239)
    nvvm_suld_2d_v4i8_zero,                    // llvm.nvvm.suld.2d.v4i8.zero (IntrinsicsNVVM.td:2239)
    nvvm_suld_3d_i16_clamp,                    // llvm.nvvm.suld.3d.i16.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i16_trap,                     // llvm.nvvm.suld.3d.i16.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i16_zero,                     // llvm.nvvm.suld.3d.i16.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i32_clamp,                    // llvm.nvvm.suld.3d.i32.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i32_trap,                     // llvm.nvvm.suld.3d.i32.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i32_zero,                     // llvm.nvvm.suld.3d.i32.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i64_clamp,                    // llvm.nvvm.suld.3d.i64.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i64_trap,                     // llvm.nvvm.suld.3d.i64.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i64_zero,                     // llvm.nvvm.suld.3d.i64.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i8_clamp,                     // llvm.nvvm.suld.3d.i8.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i8_trap,                      // llvm.nvvm.suld.3d.i8.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_i8_zero,                      // llvm.nvvm.suld.3d.i8.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i16_clamp,                  // llvm.nvvm.suld.3d.v2i16.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i16_trap,                   // llvm.nvvm.suld.3d.v2i16.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i16_zero,                   // llvm.nvvm.suld.3d.v2i16.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i32_clamp,                  // llvm.nvvm.suld.3d.v2i32.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i32_trap,                   // llvm.nvvm.suld.3d.v2i32.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i32_zero,                   // llvm.nvvm.suld.3d.v2i32.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i64_clamp,                  // llvm.nvvm.suld.3d.v2i64.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i64_trap,                   // llvm.nvvm.suld.3d.v2i64.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i64_zero,                   // llvm.nvvm.suld.3d.v2i64.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i8_clamp,                   // llvm.nvvm.suld.3d.v2i8.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i8_trap,                    // llvm.nvvm.suld.3d.v2i8.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v2i8_zero,                    // llvm.nvvm.suld.3d.v2i8.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i16_clamp,                  // llvm.nvvm.suld.3d.v4i16.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i16_trap,                   // llvm.nvvm.suld.3d.v4i16.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i16_zero,                   // llvm.nvvm.suld.3d.v4i16.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i32_clamp,                  // llvm.nvvm.suld.3d.v4i32.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i32_trap,                   // llvm.nvvm.suld.3d.v4i32.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i32_zero,                   // llvm.nvvm.suld.3d.v4i32.zero (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i8_clamp,                   // llvm.nvvm.suld.3d.v4i8.clamp (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i8_trap,                    // llvm.nvvm.suld.3d.v4i8.trap (IntrinsicsNVVM.td:2247)
    nvvm_suld_3d_v4i8_zero,                    // llvm.nvvm.suld.3d.v4i8.zero (IntrinsicsNVVM.td:2247)
    nvvm_suq_array_size,                       // llvm.nvvm.suq.array.size (IntrinsicsNVVM.td:2265)
    nvvm_suq_channel_data_type,                // llvm.nvvm.suq.channel.data.type (IntrinsicsNVVM.td:2265)
    nvvm_suq_channel_order,                    // llvm.nvvm.suq.channel.order (IntrinsicsNVVM.td:2265)
    nvvm_suq_depth,                            // llvm.nvvm.suq.depth (IntrinsicsNVVM.td:2265)
    nvvm_suq_height,                           // llvm.nvvm.suq.height (IntrinsicsNVVM.td:2265)
    nvvm_suq_width,                            // llvm.nvvm.suq.width (IntrinsicsNVVM.td:2265)
    nvvm_sust_b_1d_array_i16_clamp,            // llvm.nvvm.sust.b.1d.array.i16.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i16_trap,             // llvm.nvvm.sust.b.1d.array.i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i16_zero,             // llvm.nvvm.sust.b.1d.array.i16.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i32_clamp,            // llvm.nvvm.sust.b.1d.array.i32.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i32_trap,             // llvm.nvvm.sust.b.1d.array.i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i32_zero,             // llvm.nvvm.sust.b.1d.array.i32.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i64_clamp,            // llvm.nvvm.sust.b.1d.array.i64.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i64_trap,             // llvm.nvvm.sust.b.1d.array.i64.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i64_zero,             // llvm.nvvm.sust.b.1d.array.i64.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i8_clamp,             // llvm.nvvm.sust.b.1d.array.i8.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i8_trap,              // llvm.nvvm.sust.b.1d.array.i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_i8_zero,              // llvm.nvvm.sust.b.1d.array.i8.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i16_clamp,          // llvm.nvvm.sust.b.1d.array.v2i16.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i16_trap,           // llvm.nvvm.sust.b.1d.array.v2i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i16_zero,           // llvm.nvvm.sust.b.1d.array.v2i16.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i32_clamp,          // llvm.nvvm.sust.b.1d.array.v2i32.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i32_trap,           // llvm.nvvm.sust.b.1d.array.v2i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i32_zero,           // llvm.nvvm.sust.b.1d.array.v2i32.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i64_clamp,          // llvm.nvvm.sust.b.1d.array.v2i64.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i64_trap,           // llvm.nvvm.sust.b.1d.array.v2i64.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i64_zero,           // llvm.nvvm.sust.b.1d.array.v2i64.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i8_clamp,           // llvm.nvvm.sust.b.1d.array.v2i8.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i8_trap,            // llvm.nvvm.sust.b.1d.array.v2i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v2i8_zero,            // llvm.nvvm.sust.b.1d.array.v2i8.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i16_clamp,          // llvm.nvvm.sust.b.1d.array.v4i16.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i16_trap,           // llvm.nvvm.sust.b.1d.array.v4i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i16_zero,           // llvm.nvvm.sust.b.1d.array.v4i16.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i32_clamp,          // llvm.nvvm.sust.b.1d.array.v4i32.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i32_trap,           // llvm.nvvm.sust.b.1d.array.v4i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i32_zero,           // llvm.nvvm.sust.b.1d.array.v4i32.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i8_clamp,           // llvm.nvvm.sust.b.1d.array.v4i8.clamp (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i8_trap,            // llvm.nvvm.sust.b.1d.array.v4i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_array_v4i8_zero,            // llvm.nvvm.sust.b.1d.array.v4i8.zero (IntrinsicsNVVM.td:2282)
    nvvm_sust_b_1d_i16_clamp,                  // llvm.nvvm.sust.b.1d.i16.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i16_trap,                   // llvm.nvvm.sust.b.1d.i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i16_zero,                   // llvm.nvvm.sust.b.1d.i16.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i32_clamp,                  // llvm.nvvm.sust.b.1d.i32.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i32_trap,                   // llvm.nvvm.sust.b.1d.i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i32_zero,                   // llvm.nvvm.sust.b.1d.i32.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i64_clamp,                  // llvm.nvvm.sust.b.1d.i64.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i64_trap,                   // llvm.nvvm.sust.b.1d.i64.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i64_zero,                   // llvm.nvvm.sust.b.1d.i64.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i8_clamp,                   // llvm.nvvm.sust.b.1d.i8.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i8_trap,                    // llvm.nvvm.sust.b.1d.i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_i8_zero,                    // llvm.nvvm.sust.b.1d.i8.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i16_clamp,                // llvm.nvvm.sust.b.1d.v2i16.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i16_trap,                 // llvm.nvvm.sust.b.1d.v2i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i16_zero,                 // llvm.nvvm.sust.b.1d.v2i16.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i32_clamp,                // llvm.nvvm.sust.b.1d.v2i32.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i32_trap,                 // llvm.nvvm.sust.b.1d.v2i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i32_zero,                 // llvm.nvvm.sust.b.1d.v2i32.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i64_clamp,                // llvm.nvvm.sust.b.1d.v2i64.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i64_trap,                 // llvm.nvvm.sust.b.1d.v2i64.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i64_zero,                 // llvm.nvvm.sust.b.1d.v2i64.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i8_clamp,                 // llvm.nvvm.sust.b.1d.v2i8.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i8_trap,                  // llvm.nvvm.sust.b.1d.v2i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v2i8_zero,                  // llvm.nvvm.sust.b.1d.v2i8.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i16_clamp,                // llvm.nvvm.sust.b.1d.v4i16.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i16_trap,                 // llvm.nvvm.sust.b.1d.v4i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i16_zero,                 // llvm.nvvm.sust.b.1d.v4i16.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i32_clamp,                // llvm.nvvm.sust.b.1d.v4i32.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i32_trap,                 // llvm.nvvm.sust.b.1d.v4i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i32_zero,                 // llvm.nvvm.sust.b.1d.v4i32.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i8_clamp,                 // llvm.nvvm.sust.b.1d.v4i8.clamp (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i8_trap,                  // llvm.nvvm.sust.b.1d.v4i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_1d_v4i8_zero,                  // llvm.nvvm.sust.b.1d.v4i8.zero (IntrinsicsNVVM.td:2279)
    nvvm_sust_b_2d_array_i16_clamp,            // llvm.nvvm.sust.b.2d.array.i16.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i16_trap,             // llvm.nvvm.sust.b.2d.array.i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i16_zero,             // llvm.nvvm.sust.b.2d.array.i16.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i32_clamp,            // llvm.nvvm.sust.b.2d.array.i32.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i32_trap,             // llvm.nvvm.sust.b.2d.array.i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i32_zero,             // llvm.nvvm.sust.b.2d.array.i32.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i64_clamp,            // llvm.nvvm.sust.b.2d.array.i64.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i64_trap,             // llvm.nvvm.sust.b.2d.array.i64.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i64_zero,             // llvm.nvvm.sust.b.2d.array.i64.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i8_clamp,             // llvm.nvvm.sust.b.2d.array.i8.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i8_trap,              // llvm.nvvm.sust.b.2d.array.i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_i8_zero,              // llvm.nvvm.sust.b.2d.array.i8.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i16_clamp,          // llvm.nvvm.sust.b.2d.array.v2i16.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i16_trap,           // llvm.nvvm.sust.b.2d.array.v2i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i16_zero,           // llvm.nvvm.sust.b.2d.array.v2i16.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i32_clamp,          // llvm.nvvm.sust.b.2d.array.v2i32.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i32_trap,           // llvm.nvvm.sust.b.2d.array.v2i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i32_zero,           // llvm.nvvm.sust.b.2d.array.v2i32.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i64_clamp,          // llvm.nvvm.sust.b.2d.array.v2i64.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i64_trap,           // llvm.nvvm.sust.b.2d.array.v2i64.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i64_zero,           // llvm.nvvm.sust.b.2d.array.v2i64.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i8_clamp,           // llvm.nvvm.sust.b.2d.array.v2i8.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i8_trap,            // llvm.nvvm.sust.b.2d.array.v2i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v2i8_zero,            // llvm.nvvm.sust.b.2d.array.v2i8.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i16_clamp,          // llvm.nvvm.sust.b.2d.array.v4i16.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i16_trap,           // llvm.nvvm.sust.b.2d.array.v4i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i16_zero,           // llvm.nvvm.sust.b.2d.array.v4i16.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i32_clamp,          // llvm.nvvm.sust.b.2d.array.v4i32.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i32_trap,           // llvm.nvvm.sust.b.2d.array.v4i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i32_zero,           // llvm.nvvm.sust.b.2d.array.v4i32.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i8_clamp,           // llvm.nvvm.sust.b.2d.array.v4i8.clamp (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i8_trap,            // llvm.nvvm.sust.b.2d.array.v4i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_array_v4i8_zero,            // llvm.nvvm.sust.b.2d.array.v4i8.zero (IntrinsicsNVVM.td:2288)
    nvvm_sust_b_2d_i16_clamp,                  // llvm.nvvm.sust.b.2d.i16.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i16_trap,                   // llvm.nvvm.sust.b.2d.i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i16_zero,                   // llvm.nvvm.sust.b.2d.i16.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i32_clamp,                  // llvm.nvvm.sust.b.2d.i32.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i32_trap,                   // llvm.nvvm.sust.b.2d.i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i32_zero,                   // llvm.nvvm.sust.b.2d.i32.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i64_clamp,                  // llvm.nvvm.sust.b.2d.i64.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i64_trap,                   // llvm.nvvm.sust.b.2d.i64.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i64_zero,                   // llvm.nvvm.sust.b.2d.i64.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i8_clamp,                   // llvm.nvvm.sust.b.2d.i8.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i8_trap,                    // llvm.nvvm.sust.b.2d.i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_i8_zero,                    // llvm.nvvm.sust.b.2d.i8.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i16_clamp,                // llvm.nvvm.sust.b.2d.v2i16.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i16_trap,                 // llvm.nvvm.sust.b.2d.v2i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i16_zero,                 // llvm.nvvm.sust.b.2d.v2i16.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i32_clamp,                // llvm.nvvm.sust.b.2d.v2i32.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i32_trap,                 // llvm.nvvm.sust.b.2d.v2i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i32_zero,                 // llvm.nvvm.sust.b.2d.v2i32.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i64_clamp,                // llvm.nvvm.sust.b.2d.v2i64.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i64_trap,                 // llvm.nvvm.sust.b.2d.v2i64.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i64_zero,                 // llvm.nvvm.sust.b.2d.v2i64.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i8_clamp,                 // llvm.nvvm.sust.b.2d.v2i8.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i8_trap,                  // llvm.nvvm.sust.b.2d.v2i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v2i8_zero,                  // llvm.nvvm.sust.b.2d.v2i8.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i16_clamp,                // llvm.nvvm.sust.b.2d.v4i16.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i16_trap,                 // llvm.nvvm.sust.b.2d.v4i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i16_zero,                 // llvm.nvvm.sust.b.2d.v4i16.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i32_clamp,                // llvm.nvvm.sust.b.2d.v4i32.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i32_trap,                 // llvm.nvvm.sust.b.2d.v4i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i32_zero,                 // llvm.nvvm.sust.b.2d.v4i32.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i8_clamp,                 // llvm.nvvm.sust.b.2d.v4i8.clamp (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i8_trap,                  // llvm.nvvm.sust.b.2d.v4i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_2d_v4i8_zero,                  // llvm.nvvm.sust.b.2d.v4i8.zero (IntrinsicsNVVM.td:2285)
    nvvm_sust_b_3d_i16_clamp,                  // llvm.nvvm.sust.b.3d.i16.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i16_trap,                   // llvm.nvvm.sust.b.3d.i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i16_zero,                   // llvm.nvvm.sust.b.3d.i16.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i32_clamp,                  // llvm.nvvm.sust.b.3d.i32.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i32_trap,                   // llvm.nvvm.sust.b.3d.i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i32_zero,                   // llvm.nvvm.sust.b.3d.i32.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i64_clamp,                  // llvm.nvvm.sust.b.3d.i64.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i64_trap,                   // llvm.nvvm.sust.b.3d.i64.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i64_zero,                   // llvm.nvvm.sust.b.3d.i64.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i8_clamp,                   // llvm.nvvm.sust.b.3d.i8.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i8_trap,                    // llvm.nvvm.sust.b.3d.i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_i8_zero,                    // llvm.nvvm.sust.b.3d.i8.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i16_clamp,                // llvm.nvvm.sust.b.3d.v2i16.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i16_trap,                 // llvm.nvvm.sust.b.3d.v2i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i16_zero,                 // llvm.nvvm.sust.b.3d.v2i16.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i32_clamp,                // llvm.nvvm.sust.b.3d.v2i32.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i32_trap,                 // llvm.nvvm.sust.b.3d.v2i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i32_zero,                 // llvm.nvvm.sust.b.3d.v2i32.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i64_clamp,                // llvm.nvvm.sust.b.3d.v2i64.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i64_trap,                 // llvm.nvvm.sust.b.3d.v2i64.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i64_zero,                 // llvm.nvvm.sust.b.3d.v2i64.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i8_clamp,                 // llvm.nvvm.sust.b.3d.v2i8.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i8_trap,                  // llvm.nvvm.sust.b.3d.v2i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v2i8_zero,                  // llvm.nvvm.sust.b.3d.v2i8.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i16_clamp,                // llvm.nvvm.sust.b.3d.v4i16.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i16_trap,                 // llvm.nvvm.sust.b.3d.v4i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i16_zero,                 // llvm.nvvm.sust.b.3d.v4i16.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i32_clamp,                // llvm.nvvm.sust.b.3d.v4i32.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i32_trap,                 // llvm.nvvm.sust.b.3d.v4i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i32_zero,                 // llvm.nvvm.sust.b.3d.v4i32.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i8_clamp,                 // llvm.nvvm.sust.b.3d.v4i8.clamp (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i8_trap,                  // llvm.nvvm.sust.b.3d.v4i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_b_3d_v4i8_zero,                  // llvm.nvvm.sust.b.3d.v4i8.zero (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_1d_array_i16_trap,             // llvm.nvvm.sust.p.1d.array.i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_i32_trap,             // llvm.nvvm.sust.p.1d.array.i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_i8_trap,              // llvm.nvvm.sust.p.1d.array.i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v2i16_trap,           // llvm.nvvm.sust.p.1d.array.v2i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v2i32_trap,           // llvm.nvvm.sust.p.1d.array.v2i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v2i8_trap,            // llvm.nvvm.sust.p.1d.array.v2i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v4i16_trap,           // llvm.nvvm.sust.p.1d.array.v4i16.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v4i32_trap,           // llvm.nvvm.sust.p.1d.array.v4i32.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_array_v4i8_trap,            // llvm.nvvm.sust.p.1d.array.v4i8.trap (IntrinsicsNVVM.td:2282)
    nvvm_sust_p_1d_i16_trap,                   // llvm.nvvm.sust.p.1d.i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_i32_trap,                   // llvm.nvvm.sust.p.1d.i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_i8_trap,                    // llvm.nvvm.sust.p.1d.i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v2i16_trap,                 // llvm.nvvm.sust.p.1d.v2i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v2i32_trap,                 // llvm.nvvm.sust.p.1d.v2i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v2i8_trap,                  // llvm.nvvm.sust.p.1d.v2i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v4i16_trap,                 // llvm.nvvm.sust.p.1d.v4i16.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v4i32_trap,                 // llvm.nvvm.sust.p.1d.v4i32.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_1d_v4i8_trap,                  // llvm.nvvm.sust.p.1d.v4i8.trap (IntrinsicsNVVM.td:2279)
    nvvm_sust_p_2d_array_i16_trap,             // llvm.nvvm.sust.p.2d.array.i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_i32_trap,             // llvm.nvvm.sust.p.2d.array.i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_i8_trap,              // llvm.nvvm.sust.p.2d.array.i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v2i16_trap,           // llvm.nvvm.sust.p.2d.array.v2i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v2i32_trap,           // llvm.nvvm.sust.p.2d.array.v2i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v2i8_trap,            // llvm.nvvm.sust.p.2d.array.v2i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v4i16_trap,           // llvm.nvvm.sust.p.2d.array.v4i16.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v4i32_trap,           // llvm.nvvm.sust.p.2d.array.v4i32.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_array_v4i8_trap,            // llvm.nvvm.sust.p.2d.array.v4i8.trap (IntrinsicsNVVM.td:2288)
    nvvm_sust_p_2d_i16_trap,                   // llvm.nvvm.sust.p.2d.i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_i32_trap,                   // llvm.nvvm.sust.p.2d.i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_i8_trap,                    // llvm.nvvm.sust.p.2d.i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v2i16_trap,                 // llvm.nvvm.sust.p.2d.v2i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v2i32_trap,                 // llvm.nvvm.sust.p.2d.v2i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v2i8_trap,                  // llvm.nvvm.sust.p.2d.v2i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v4i16_trap,                 // llvm.nvvm.sust.p.2d.v4i16.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v4i32_trap,                 // llvm.nvvm.sust.p.2d.v4i32.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_2d_v4i8_trap,                  // llvm.nvvm.sust.p.2d.v4i8.trap (IntrinsicsNVVM.td:2285)
    nvvm_sust_p_3d_i16_trap,                   // llvm.nvvm.sust.p.3d.i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_i32_trap,                   // llvm.nvvm.sust.p.3d.i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_i8_trap,                    // llvm.nvvm.sust.p.3d.i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v2i16_trap,                 // llvm.nvvm.sust.p.3d.v2i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v2i32_trap,                 // llvm.nvvm.sust.p.3d.v2i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v2i8_trap,                  // llvm.nvvm.sust.p.3d.v2i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v4i16_trap,                 // llvm.nvvm.sust.p.3d.v4i16.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v4i32_trap,                 // llvm.nvvm.sust.p.3d.v4i32.trap (IntrinsicsNVVM.td:2291)
    nvvm_sust_p_3d_v4i8_trap,                  // llvm.nvvm.sust.p.3d.v4i8.trap (IntrinsicsNVVM.td:2291)
    nvvm_tcgen05_alloc_cg1,                    // llvm.nvvm.tcgen05.alloc.cg1 (IntrinsicsNVVM.td:3039)
    nvvm_tcgen05_alloc_cg2,                    // llvm.nvvm.tcgen05.alloc.cg2 (IntrinsicsNVVM.td:3039)
    nvvm_tcgen05_alloc_shared_cg1,             // llvm.nvvm.tcgen05.alloc.shared.cg1 (IntrinsicsNVVM.td:3045)
    nvvm_tcgen05_alloc_shared_cg2,             // llvm.nvvm.tcgen05.alloc.shared.cg2 (IntrinsicsNVVM.td:3045)
    nvvm_tcgen05_commit_cg1,                   // llvm.nvvm.tcgen05.commit.cg1 (IntrinsicsNVVM.td:3060)
    nvvm_tcgen05_commit_cg2,                   // llvm.nvvm.tcgen05.commit.cg2 (IntrinsicsNVVM.td:3060)
    nvvm_tcgen05_commit_mc_cg1,                // llvm.nvvm.tcgen05.commit.mc.cg1 (IntrinsicsNVVM.td:3070)
    nvvm_tcgen05_commit_mc_cg2,                // llvm.nvvm.tcgen05.commit.mc.cg2 (IntrinsicsNVVM.td:3070)
    nvvm_tcgen05_commit_mc_shared_cg1,         // llvm.nvvm.tcgen05.commit.mc.shared.cg1 (IntrinsicsNVVM.td:3075)
    nvvm_tcgen05_commit_mc_shared_cg2,         // llvm.nvvm.tcgen05.commit.mc.shared.cg2 (IntrinsicsNVVM.td:3075)
    nvvm_tcgen05_commit_shared_cg1,            // llvm.nvvm.tcgen05.commit.shared.cg1 (IntrinsicsNVVM.td:3065)
    nvvm_tcgen05_commit_shared_cg2,            // llvm.nvvm.tcgen05.commit.shared.cg2 (IntrinsicsNVVM.td:3065)
    nvvm_tcgen05_cp_128x128b_b4x16_p64_cg1,    // llvm.nvvm.tcgen05.cp.128x128b.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x128b_b4x16_p64_cg2,    // llvm.nvvm.tcgen05.cp.128x128b.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x128b_b6x16_p32_cg1,    // llvm.nvvm.tcgen05.cp.128x128b.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x128b_b6x16_p32_cg2,    // llvm.nvvm.tcgen05.cp.128x128b.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x128b_cg1,              // llvm.nvvm.tcgen05.cp.128x128b.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x128b_cg2,              // llvm.nvvm.tcgen05.cp.128x128b.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_b4x16_p64_cg1,    // llvm.nvvm.tcgen05.cp.128x256b.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_b4x16_p64_cg2,    // llvm.nvvm.tcgen05.cp.128x256b.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_b6x16_p32_cg1,    // llvm.nvvm.tcgen05.cp.128x256b.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_b6x16_p32_cg2,    // llvm.nvvm.tcgen05.cp.128x256b.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_cg1,              // llvm.nvvm.tcgen05.cp.128x256b.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_128x256b_cg2,              // llvm.nvvm.tcgen05.cp.128x256b.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_b4x16_p64_cg1,  // llvm.nvvm.tcgen05.cp.32x128b_warpx4.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2,  // llvm.nvvm.tcgen05.cp.32x128b_warpx4.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_b6x16_p32_cg1,  // llvm.nvvm.tcgen05.cp.32x128b_warpx4.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2,  // llvm.nvvm.tcgen05.cp.32x128b_warpx4.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_cg1,        // llvm.nvvm.tcgen05.cp.32x128b_warpx4.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_32x128b_warpx4_cg2,        // llvm.nvvm.tcgen05.cp.32x128b_warpx4.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_b4x16_p64_cg1,      // llvm.nvvm.tcgen05.cp.4x256b.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_b4x16_p64_cg2,      // llvm.nvvm.tcgen05.cp.4x256b.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_b6x16_p32_cg1,      // llvm.nvvm.tcgen05.cp.4x256b.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_b6x16_p32_cg2,      // llvm.nvvm.tcgen05.cp.4x256b.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_cg1,                // llvm.nvvm.tcgen05.cp.4x256b.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_4x256b_cg2,                // llvm.nvvm.tcgen05.cp.4x256b.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_01_23_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b4x16_p64.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b4x16_p64.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b6x16_p32.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b6x16_p32.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_cg1,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.cg1 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_cp_64x128b_warpx2_02_13_cg2,  // llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.cg2 (IntrinsicsNVVM.td:3109)
    nvvm_tcgen05_dealloc_cg1,                  // llvm.nvvm.tcgen05.dealloc.cg1 (IntrinsicsNVVM.td:3051)
    nvvm_tcgen05_dealloc_cg2,                  // llvm.nvvm.tcgen05.dealloc.cg2 (IntrinsicsNVVM.td:3051)
    nvvm_tcgen05_fence_after_thread_sync,      // llvm.nvvm.tcgen05.fence.after.thread.sync (IntrinsicsNVVM.td:3095)
    nvvm_tcgen05_fence_before_thread_sync,     // llvm.nvvm.tcgen05.fence.before.thread.sync (IntrinsicsNVVM.td:3093)
    nvvm_tcgen05_ld_16x128b_x1,                // llvm.nvvm.tcgen05.ld.16x128b.x1 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x16,               // llvm.nvvm.tcgen05.ld.16x128b.x16 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x2,                // llvm.nvvm.tcgen05.ld.16x128b.x2 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x32,               // llvm.nvvm.tcgen05.ld.16x128b.x32 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x4,                // llvm.nvvm.tcgen05.ld.16x128b.x4 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x64,               // llvm.nvvm.tcgen05.ld.16x128b.x64 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x128b_x8,                // llvm.nvvm.tcgen05.ld.16x128b.x8 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x1,                // llvm.nvvm.tcgen05.ld.16x256b.x1 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x16,               // llvm.nvvm.tcgen05.ld.16x256b.x16 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x2,                // llvm.nvvm.tcgen05.ld.16x256b.x2 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x32,               // llvm.nvvm.tcgen05.ld.16x256b.x32 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x4,                // llvm.nvvm.tcgen05.ld.16x256b.x4 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x256b_x8,                // llvm.nvvm.tcgen05.ld.16x256b.x8 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x1,               // llvm.nvvm.tcgen05.ld.16x32bx2.x1 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x128,             // llvm.nvvm.tcgen05.ld.16x32bx2.x128 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x16,              // llvm.nvvm.tcgen05.ld.16x32bx2.x16 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x2,               // llvm.nvvm.tcgen05.ld.16x32bx2.x2 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x32,              // llvm.nvvm.tcgen05.ld.16x32bx2.x32 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x4,               // llvm.nvvm.tcgen05.ld.16x32bx2.x4 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x64,              // llvm.nvvm.tcgen05.ld.16x32bx2.x64 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x32bx2_x8,               // llvm.nvvm.tcgen05.ld.16x32bx2.x8 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x1,                 // llvm.nvvm.tcgen05.ld.16x64b.x1 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x128,               // llvm.nvvm.tcgen05.ld.16x64b.x128 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x16,                // llvm.nvvm.tcgen05.ld.16x64b.x16 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x2,                 // llvm.nvvm.tcgen05.ld.16x64b.x2 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x32,                // llvm.nvvm.tcgen05.ld.16x64b.x32 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x4,                 // llvm.nvvm.tcgen05.ld.16x64b.x4 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x64,                // llvm.nvvm.tcgen05.ld.16x64b.x64 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_16x64b_x8,                 // llvm.nvvm.tcgen05.ld.16x64b.x8 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x1,                 // llvm.nvvm.tcgen05.ld.32x32b.x1 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x128,               // llvm.nvvm.tcgen05.ld.32x32b.x128 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x16,                // llvm.nvvm.tcgen05.ld.32x32b.x16 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x2,                 // llvm.nvvm.tcgen05.ld.32x32b.x2 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x32,                // llvm.nvvm.tcgen05.ld.32x32b.x32 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x4,                 // llvm.nvvm.tcgen05.ld.32x32b.x4 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x64,                // llvm.nvvm.tcgen05.ld.32x32b.x64 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_ld_32x32b_x8,                 // llvm.nvvm.tcgen05.ld.32x32b.x8 (IntrinsicsNVVM.td:3144)
    nvvm_tcgen05_mma_shared,                   // llvm.nvvm.tcgen05.mma.shared (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_shared_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_shared_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.shared.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_shared_mxf4_block_scale,  // llvm.nvvm.tcgen05.mma.shared.mxf4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_mxf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.shared.mxf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_mxf4nvf4_block_scale_block16,  // llvm.nvvm.tcgen05.mma.shared.mxf4nvf4.block_scale.block16 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_mxf4nvf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.shared.mxf4nvf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_mxf8f6f4_block_scale,  // llvm.nvvm.tcgen05.mma.shared.mxf8f6f4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_mxf8f6f4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.shared.mxf8f6f4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_shared_scale_d,           // llvm.nvvm.tcgen05.mma.shared.scale_d (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_shared_scale_d_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.shared.scale_d.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_shared_scale_d_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.shared.scale_d.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_shared,                // llvm.nvvm.tcgen05.mma.sp.shared (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_shared_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.sp.shared.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_shared_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.sp.shared.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_shared_mxf4_block_scale,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_mxf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_mxf4nvf4_block_scale_block16,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf4nvf4.block_scale.block16 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_mxf4nvf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf4nvf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_mxf8f6f4_block_scale,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf8f6f4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_mxf8f6f4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.shared.mxf8f6f4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_shared_scale_d,        // llvm.nvvm.tcgen05.mma.sp.shared.scale_d (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_shared_scale_d_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.sp.shared.scale_d.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_shared_scale_d_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.sp.shared.scale_d.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor,                // llvm.nvvm.tcgen05.mma.sp.tensor (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_tensor_ashift,         // llvm.nvvm.tcgen05.mma.sp.tensor.ashift (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_tensor_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.sp.tensor.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_disable_output_lane_cg1_ashift,  // llvm.nvvm.tcgen05.mma.sp.tensor.disable_output_lane.cg1.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.sp.tensor.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_disable_output_lane_cg2_ashift,  // llvm.nvvm.tcgen05.mma.sp.tensor.disable_output_lane.cg2.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_mxf4_block_scale,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_mxf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_mxf4nvf4_block_scale_block16,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf4nvf4.block_scale.block16 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_mxf4nvf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf4nvf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_mxf8f6f4_block_scale,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf8f6f4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_mxf8f6f4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.sp.tensor.mxf8f6f4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_sp_tensor_scale_d,        // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_tensor_scale_d_ashift,  // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d.ashift (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_sp_tensor_scale_d_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_scale_d_disable_output_lane_cg1_ashift,  // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d.disable_output_lane.cg1.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_scale_d_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_sp_tensor_scale_d_disable_output_lane_cg2_ashift,  // llvm.nvvm.tcgen05.mma.sp.tensor.scale_d.disable_output_lane.cg2.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor,                   // llvm.nvvm.tcgen05.mma.tensor (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_tensor_ashift,            // llvm.nvvm.tcgen05.mma.tensor.ashift (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_tensor_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.tensor.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_disable_output_lane_cg1_ashift,  // llvm.nvvm.tcgen05.mma.tensor.disable_output_lane.cg1.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.tensor.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_disable_output_lane_cg2_ashift,  // llvm.nvvm.tcgen05.mma.tensor.disable_output_lane.cg2.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_mxf4_block_scale,  // llvm.nvvm.tcgen05.mma.tensor.mxf4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_mxf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.tensor.mxf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_mxf4nvf4_block_scale_block16,  // llvm.nvvm.tcgen05.mma.tensor.mxf4nvf4.block_scale.block16 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_mxf4nvf4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.tensor.mxf4nvf4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_mxf8f6f4_block_scale,  // llvm.nvvm.tcgen05.mma.tensor.mxf8f6f4.block_scale (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_mxf8f6f4_block_scale_block32,  // llvm.nvvm.tcgen05.mma.tensor.mxf8f6f4.block_scale.block32 (IntrinsicsNVVM.td:3297)
    nvvm_tcgen05_mma_tensor_scale_d,           // llvm.nvvm.tcgen05.mma.tensor.scale_d (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_tensor_scale_d_ashift,    // llvm.nvvm.tcgen05.mma.tensor.scale_d.ashift (IntrinsicsNVVM.td:3234)
    nvvm_tcgen05_mma_tensor_scale_d_disable_output_lane_cg1,  // llvm.nvvm.tcgen05.mma.tensor.scale_d.disable_output_lane.cg1 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_scale_d_disable_output_lane_cg1_ashift,  // llvm.nvvm.tcgen05.mma.tensor.scale_d.disable_output_lane.cg1.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_scale_d_disable_output_lane_cg2,  // llvm.nvvm.tcgen05.mma.tensor.scale_d.disable_output_lane.cg2 (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_tensor_scale_d_disable_output_lane_cg2_ashift,  // llvm.nvvm.tcgen05.mma.tensor.scale_d.disable_output_lane.cg2.ashift (IntrinsicsNVVM.td:3271)
    nvvm_tcgen05_mma_ws_shared,                // llvm.nvvm.tcgen05.mma.ws.shared (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_shared_zero_col_mask,  // llvm.nvvm.tcgen05.mma.ws.shared.zero_col_mask (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_sp_shared,             // llvm.nvvm.tcgen05.mma.ws.sp.shared (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_sp_shared_zero_col_mask,  // llvm.nvvm.tcgen05.mma.ws.sp.shared.zero_col_mask (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_sp_tensor,             // llvm.nvvm.tcgen05.mma.ws.sp.tensor (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_sp_tensor_zero_col_mask,  // llvm.nvvm.tcgen05.mma.ws.sp.tensor.zero_col_mask (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_tensor,                // llvm.nvvm.tcgen05.mma.ws.tensor (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_mma_ws_tensor_zero_col_mask,  // llvm.nvvm.tcgen05.mma.ws.tensor.zero_col_mask (IntrinsicsNVVM.td:3330)
    nvvm_tcgen05_relinq_alloc_permit_cg1,      // llvm.nvvm.tcgen05.relinq.alloc.permit.cg1 (IntrinsicsNVVM.td:3057)
    nvvm_tcgen05_relinq_alloc_permit_cg2,      // llvm.nvvm.tcgen05.relinq.alloc.permit.cg2 (IntrinsicsNVVM.td:3057)
    nvvm_tcgen05_shift_down_cg1,               // llvm.nvvm.tcgen05.shift.down.cg1 (IntrinsicsNVVM.td:3080)
    nvvm_tcgen05_shift_down_cg2,               // llvm.nvvm.tcgen05.shift.down.cg2 (IntrinsicsNVVM.td:3080)
    nvvm_tcgen05_st_16x128b_x1,                // llvm.nvvm.tcgen05.st.16x128b.x1 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x16,               // llvm.nvvm.tcgen05.st.16x128b.x16 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x2,                // llvm.nvvm.tcgen05.st.16x128b.x2 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x32,               // llvm.nvvm.tcgen05.st.16x128b.x32 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x4,                // llvm.nvvm.tcgen05.st.16x128b.x4 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x64,               // llvm.nvvm.tcgen05.st.16x128b.x64 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x128b_x8,                // llvm.nvvm.tcgen05.st.16x128b.x8 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x1,                // llvm.nvvm.tcgen05.st.16x256b.x1 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x16,               // llvm.nvvm.tcgen05.st.16x256b.x16 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x2,                // llvm.nvvm.tcgen05.st.16x256b.x2 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x32,               // llvm.nvvm.tcgen05.st.16x256b.x32 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x4,                // llvm.nvvm.tcgen05.st.16x256b.x4 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x256b_x8,                // llvm.nvvm.tcgen05.st.16x256b.x8 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x1,               // llvm.nvvm.tcgen05.st.16x32bx2.x1 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x128,             // llvm.nvvm.tcgen05.st.16x32bx2.x128 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x16,              // llvm.nvvm.tcgen05.st.16x32bx2.x16 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x2,               // llvm.nvvm.tcgen05.st.16x32bx2.x2 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x32,              // llvm.nvvm.tcgen05.st.16x32bx2.x32 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x4,               // llvm.nvvm.tcgen05.st.16x32bx2.x4 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x64,              // llvm.nvvm.tcgen05.st.16x32bx2.x64 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x32bx2_x8,               // llvm.nvvm.tcgen05.st.16x32bx2.x8 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x1,                 // llvm.nvvm.tcgen05.st.16x64b.x1 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x128,               // llvm.nvvm.tcgen05.st.16x64b.x128 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x16,                // llvm.nvvm.tcgen05.st.16x64b.x16 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x2,                 // llvm.nvvm.tcgen05.st.16x64b.x2 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x32,                // llvm.nvvm.tcgen05.st.16x64b.x32 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x4,                 // llvm.nvvm.tcgen05.st.16x64b.x4 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x64,                // llvm.nvvm.tcgen05.st.16x64b.x64 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_16x64b_x8,                 // llvm.nvvm.tcgen05.st.16x64b.x8 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x1,                 // llvm.nvvm.tcgen05.st.32x32b.x1 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x128,               // llvm.nvvm.tcgen05.st.32x32b.x128 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x16,                // llvm.nvvm.tcgen05.st.32x32b.x16 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x2,                 // llvm.nvvm.tcgen05.st.32x32b.x2 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x32,                // llvm.nvvm.tcgen05.st.32x32b.x32 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x4,                 // llvm.nvvm.tcgen05.st.32x32b.x4 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x64,                // llvm.nvvm.tcgen05.st.32x32b.x64 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_st_32x32b_x8,                 // llvm.nvvm.tcgen05.st.32x32b.x8 (IntrinsicsNVVM.td:3146)
    nvvm_tcgen05_wait_ld,                      // llvm.nvvm.tcgen05.wait.ld (IntrinsicsNVVM.td:3087)
    nvvm_tcgen05_wait_st,                      // llvm.nvvm.tcgen05.wait.st (IntrinsicsNVVM.td:3089)
    nvvm_tensormap_replace_box_dim,            // llvm.nvvm.tensormap.replace.box.dim (IntrinsicsNVVM.td:3353)
    nvvm_tensormap_replace_element_stride,     // llvm.nvvm.tensormap.replace.element.stride (IntrinsicsNVVM.td:3353)
    nvvm_tensormap_replace_elemtype,           // llvm.nvvm.tensormap.replace.elemtype (IntrinsicsNVVM.td:3358)
    nvvm_tensormap_replace_fill_mode,          // llvm.nvvm.tensormap.replace.fill.mode (IntrinsicsNVVM.td:3382)
    nvvm_tensormap_replace_global_address,     // llvm.nvvm.tensormap.replace.global.address (IntrinsicsNVVM.td:3342)
    nvvm_tensormap_replace_global_dim,         // llvm.nvvm.tensormap.replace.global.dim (IntrinsicsNVVM.td:3353)
    nvvm_tensormap_replace_global_stride,      // llvm.nvvm.tensormap.replace.global.stride (IntrinsicsNVVM.td:3350)
    nvvm_tensormap_replace_interleave_layout,  // llvm.nvvm.tensormap.replace.interleave.layout (IntrinsicsNVVM.td:3364)
    nvvm_tensormap_replace_rank,               // llvm.nvvm.tensormap.replace.rank (IntrinsicsNVVM.td:3344)
    nvvm_tensormap_replace_swizzle_atomicity,  // llvm.nvvm.tensormap.replace.swizzle.atomicity (IntrinsicsNVVM.td:3376)
    nvvm_tensormap_replace_swizzle_mode,       // llvm.nvvm.tensormap.replace.swizzle.mode (IntrinsicsNVVM.td:3370)
    nvvm_tex_1d_array_grad_v4f32_f32,          // llvm.nvvm.tex.1d.array.grad.v4f32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_array_grad_v4s32_f32,          // llvm.nvvm.tex.1d.array.grad.v4s32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_array_grad_v4u32_f32,          // llvm.nvvm.tex.1d.array.grad.v4u32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_array_level_v4f32_f32,         // llvm.nvvm.tex.1d.array.level.v4f32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_array_level_v4s32_f32,         // llvm.nvvm.tex.1d.array.level.v4s32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_array_level_v4u32_f32,         // llvm.nvvm.tex.1d.array.level.v4u32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_array_v4f32_f32,               // llvm.nvvm.tex.1d.array.v4f32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_array_v4f32_s32,               // llvm.nvvm.tex.1d.array.v4f32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_1d_array_v4s32_f32,               // llvm.nvvm.tex.1d.array.v4s32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_array_v4s32_s32,               // llvm.nvvm.tex.1d.array.v4s32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_1d_array_v4u32_f32,               // llvm.nvvm.tex.1d.array.v4u32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_array_v4u32_s32,               // llvm.nvvm.tex.1d.array.v4u32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_1d_grad_v4f32_f32,                // llvm.nvvm.tex.1d.grad.v4f32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_grad_v4s32_f32,                // llvm.nvvm.tex.1d.grad.v4s32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_grad_v4u32_f32,                // llvm.nvvm.tex.1d.grad.v4u32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_1d_level_v4f32_f32,               // llvm.nvvm.tex.1d.level.v4f32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_level_v4s32_f32,               // llvm.nvvm.tex.1d.level.v4s32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_level_v4u32_f32,               // llvm.nvvm.tex.1d.level.v4u32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_1d_v4f32_f32,                     // llvm.nvvm.tex.1d.v4f32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_v4f32_s32,                     // llvm.nvvm.tex.1d.v4f32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_1d_v4s32_f32,                     // llvm.nvvm.tex.1d.v4s32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_v4s32_s32,                     // llvm.nvvm.tex.1d.v4s32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_1d_v4u32_f32,                     // llvm.nvvm.tex.1d.v4u32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_1d_v4u32_s32,                     // llvm.nvvm.tex.1d.v4u32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_2d_array_grad_v4f32_f32,          // llvm.nvvm.tex.2d.array.grad.v4f32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_array_grad_v4s32_f32,          // llvm.nvvm.tex.2d.array.grad.v4s32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_array_grad_v4u32_f32,          // llvm.nvvm.tex.2d.array.grad.v4u32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_array_level_v4f32_f32,         // llvm.nvvm.tex.2d.array.level.v4f32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_array_level_v4s32_f32,         // llvm.nvvm.tex.2d.array.level.v4s32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_array_level_v4u32_f32,         // llvm.nvvm.tex.2d.array.level.v4u32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_array_v4f32_f32,               // llvm.nvvm.tex.2d.array.v4f32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_array_v4f32_s32,               // llvm.nvvm.tex.2d.array.v4f32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_2d_array_v4s32_f32,               // llvm.nvvm.tex.2d.array.v4s32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_array_v4s32_s32,               // llvm.nvvm.tex.2d.array.v4s32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_2d_array_v4u32_f32,               // llvm.nvvm.tex.2d.array.v4u32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_array_v4u32_s32,               // llvm.nvvm.tex.2d.array.v4u32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_2d_grad_v4f32_f32,                // llvm.nvvm.tex.2d.grad.v4f32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_grad_v4s32_f32,                // llvm.nvvm.tex.2d.grad.v4s32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_grad_v4u32_f32,                // llvm.nvvm.tex.2d.grad.v4u32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_2d_level_v4f32_f32,               // llvm.nvvm.tex.2d.level.v4f32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_level_v4s32_f32,               // llvm.nvvm.tex.2d.level.v4s32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_level_v4u32_f32,               // llvm.nvvm.tex.2d.level.v4u32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_2d_v4f32_f32,                     // llvm.nvvm.tex.2d.v4f32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_v4f32_s32,                     // llvm.nvvm.tex.2d.v4f32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_2d_v4s32_f32,                     // llvm.nvvm.tex.2d.v4s32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_v4s32_s32,                     // llvm.nvvm.tex.2d.v4s32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_2d_v4u32_f32,                     // llvm.nvvm.tex.2d.v4u32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_2d_v4u32_s32,                     // llvm.nvvm.tex.2d.v4u32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_3d_grad_v4f32_f32,                // llvm.nvvm.tex.3d.grad.v4f32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_3d_grad_v4s32_f32,                // llvm.nvvm.tex.3d.grad.v4s32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_3d_grad_v4u32_f32,                // llvm.nvvm.tex.3d.grad.v4u32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_3d_level_v4f32_f32,               // llvm.nvvm.tex.3d.level.v4f32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_3d_level_v4s32_f32,               // llvm.nvvm.tex.3d.level.v4s32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_3d_level_v4u32_f32,               // llvm.nvvm.tex.3d.level.v4u32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_3d_v4f32_f32,                     // llvm.nvvm.tex.3d.v4f32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_3d_v4f32_s32,                     // llvm.nvvm.tex.3d.v4f32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_3d_v4s32_f32,                     // llvm.nvvm.tex.3d.v4s32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_3d_v4s32_s32,                     // llvm.nvvm.tex.3d.v4s32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_3d_v4u32_f32,                     // llvm.nvvm.tex.3d.v4u32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_3d_v4u32_s32,                     // llvm.nvvm.tex.3d.v4u32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_cube_array_level_v4f32_f32,       // llvm.nvvm.tex.cube.array.level.v4f32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_array_level_v4s32_f32,       // llvm.nvvm.tex.cube.array.level.v4s32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_array_level_v4u32_f32,       // llvm.nvvm.tex.cube.array.level.v4u32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_array_v4f32_f32,             // llvm.nvvm.tex.cube.array.v4f32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_cube_array_v4s32_f32,             // llvm.nvvm.tex.cube.array.v4s32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_cube_array_v4u32_f32,             // llvm.nvvm.tex.cube.array.v4u32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_cube_level_v4f32_f32,             // llvm.nvvm.tex.cube.level.v4f32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_level_v4s32_f32,             // llvm.nvvm.tex.cube.level.v4s32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_level_v4u32_f32,             // llvm.nvvm.tex.cube.level.v4u32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_cube_v4f32_f32,                   // llvm.nvvm.tex.cube.v4f32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_cube_v4s32_f32,                   // llvm.nvvm.tex.cube.v4s32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_cube_v4u32_f32,                   // llvm.nvvm.tex.cube.v4u32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_1d_array_grad_v4f32_f32,  // llvm.nvvm.tex.unified.1d.array.grad.v4f32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_array_grad_v4s32_f32,  // llvm.nvvm.tex.unified.1d.array.grad.v4s32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_array_grad_v4u32_f32,  // llvm.nvvm.tex.unified.1d.array.grad.v4u32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_array_level_v4f32_f32,  // llvm.nvvm.tex.unified.1d.array.level.v4f32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_array_level_v4s32_f32,  // llvm.nvvm.tex.unified.1d.array.level.v4s32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_array_level_v4u32_f32,  // llvm.nvvm.tex.unified.1d.array.level.v4u32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_array_v4f32_f32,       // llvm.nvvm.tex.unified.1d.array.v4f32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_array_v4f32_s32,       // llvm.nvvm.tex.unified.1d.array.v4f32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_1d_array_v4s32_f32,       // llvm.nvvm.tex.unified.1d.array.v4s32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_array_v4s32_s32,       // llvm.nvvm.tex.unified.1d.array.v4s32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_1d_array_v4u32_f32,       // llvm.nvvm.tex.unified.1d.array.v4u32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_array_v4u32_s32,       // llvm.nvvm.tex.unified.1d.array.v4u32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_1d_grad_v4f32_f32,        // llvm.nvvm.tex.unified.1d.grad.v4f32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_grad_v4s32_f32,        // llvm.nvvm.tex.unified.1d.grad.v4s32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_grad_v4u32_f32,        // llvm.nvvm.tex.unified.1d.grad.v4u32.f32 (IntrinsicsNVVM.td:2181)
    nvvm_tex_unified_1d_level_v4f32_f32,       // llvm.nvvm.tex.unified.1d.level.v4f32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_level_v4s32_f32,       // llvm.nvvm.tex.unified.1d.level.v4s32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_level_v4u32_f32,       // llvm.nvvm.tex.unified.1d.level.v4u32.f32 (IntrinsicsNVVM.td:2179)
    nvvm_tex_unified_1d_v4f32_f32,             // llvm.nvvm.tex.unified.1d.v4f32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_v4f32_s32,             // llvm.nvvm.tex.unified.1d.v4f32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_1d_v4s32_f32,             // llvm.nvvm.tex.unified.1d.v4s32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_v4s32_s32,             // llvm.nvvm.tex.unified.1d.v4s32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_1d_v4u32_f32,             // llvm.nvvm.tex.unified.1d.v4u32.f32 (IntrinsicsNVVM.td:2177)
    nvvm_tex_unified_1d_v4u32_s32,             // llvm.nvvm.tex.unified.1d.v4u32.s32 (IntrinsicsNVVM.td:2175)
    nvvm_tex_unified_2d_array_grad_v4f32_f32,  // llvm.nvvm.tex.unified.2d.array.grad.v4f32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_array_grad_v4s32_f32,  // llvm.nvvm.tex.unified.2d.array.grad.v4s32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_array_grad_v4u32_f32,  // llvm.nvvm.tex.unified.2d.array.grad.v4u32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_array_level_v4f32_f32,  // llvm.nvvm.tex.unified.2d.array.level.v4f32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_array_level_v4s32_f32,  // llvm.nvvm.tex.unified.2d.array.level.v4s32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_array_level_v4u32_f32,  // llvm.nvvm.tex.unified.2d.array.level.v4u32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_array_v4f32_f32,       // llvm.nvvm.tex.unified.2d.array.v4f32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_array_v4f32_s32,       // llvm.nvvm.tex.unified.2d.array.v4f32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_2d_array_v4s32_f32,       // llvm.nvvm.tex.unified.2d.array.v4s32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_array_v4s32_s32,       // llvm.nvvm.tex.unified.2d.array.v4s32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_2d_array_v4u32_f32,       // llvm.nvvm.tex.unified.2d.array.v4u32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_array_v4u32_s32,       // llvm.nvvm.tex.unified.2d.array.v4u32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_2d_grad_v4f32_f32,        // llvm.nvvm.tex.unified.2d.grad.v4f32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_grad_v4s32_f32,        // llvm.nvvm.tex.unified.2d.grad.v4s32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_grad_v4u32_f32,        // llvm.nvvm.tex.unified.2d.grad.v4u32.f32 (IntrinsicsNVVM.td:2190)
    nvvm_tex_unified_2d_level_v4f32_f32,       // llvm.nvvm.tex.unified.2d.level.v4f32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_level_v4s32_f32,       // llvm.nvvm.tex.unified.2d.level.v4s32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_level_v4u32_f32,       // llvm.nvvm.tex.unified.2d.level.v4u32.f32 (IntrinsicsNVVM.td:2188)
    nvvm_tex_unified_2d_v4f32_f32,             // llvm.nvvm.tex.unified.2d.v4f32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_v4f32_s32,             // llvm.nvvm.tex.unified.2d.v4f32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_2d_v4s32_f32,             // llvm.nvvm.tex.unified.2d.v4s32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_v4s32_s32,             // llvm.nvvm.tex.unified.2d.v4s32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_2d_v4u32_f32,             // llvm.nvvm.tex.unified.2d.v4u32.f32 (IntrinsicsNVVM.td:2186)
    nvvm_tex_unified_2d_v4u32_s32,             // llvm.nvvm.tex.unified.2d.v4u32.s32 (IntrinsicsNVVM.td:2184)
    nvvm_tex_unified_3d_grad_v4f32_f32,        // llvm.nvvm.tex.unified.3d.grad.v4f32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_unified_3d_grad_v4s32_f32,        // llvm.nvvm.tex.unified.3d.grad.v4s32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_unified_3d_grad_v4u32_f32,        // llvm.nvvm.tex.unified.3d.grad.v4u32.f32 (IntrinsicsNVVM.td:2200)
    nvvm_tex_unified_3d_level_v4f32_f32,       // llvm.nvvm.tex.unified.3d.level.v4f32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_unified_3d_level_v4s32_f32,       // llvm.nvvm.tex.unified.3d.level.v4s32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_unified_3d_level_v4u32_f32,       // llvm.nvvm.tex.unified.3d.level.v4u32.f32 (IntrinsicsNVVM.td:2198)
    nvvm_tex_unified_3d_v4f32_f32,             // llvm.nvvm.tex.unified.3d.v4f32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_unified_3d_v4f32_s32,             // llvm.nvvm.tex.unified.3d.v4f32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_unified_3d_v4s32_f32,             // llvm.nvvm.tex.unified.3d.v4s32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_unified_3d_v4s32_s32,             // llvm.nvvm.tex.unified.3d.v4s32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_unified_3d_v4u32_f32,             // llvm.nvvm.tex.unified.3d.v4u32.f32 (IntrinsicsNVVM.td:2196)
    nvvm_tex_unified_3d_v4u32_s32,             // llvm.nvvm.tex.unified.3d.v4u32.s32 (IntrinsicsNVVM.td:2194)
    nvvm_tex_unified_cube_array_grad_v4f32_f32,  // llvm.nvvm.tex.unified.cube.array.grad.v4f32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_array_grad_v4s32_f32,  // llvm.nvvm.tex.unified.cube.array.grad.v4s32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_array_grad_v4u32_f32,  // llvm.nvvm.tex.unified.cube.array.grad.v4u32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_array_level_v4f32_f32,  // llvm.nvvm.tex.unified.cube.array.level.v4f32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_array_level_v4s32_f32,  // llvm.nvvm.tex.unified.cube.array.level.v4s32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_array_level_v4u32_f32,  // llvm.nvvm.tex.unified.cube.array.level.v4u32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_array_v4f32_f32,     // llvm.nvvm.tex.unified.cube.array.v4f32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_cube_array_v4s32_f32,     // llvm.nvvm.tex.unified.cube.array.v4s32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_cube_array_v4u32_f32,     // llvm.nvvm.tex.unified.cube.array.v4u32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_cube_grad_v4f32_f32,      // llvm.nvvm.tex.unified.cube.grad.v4f32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_grad_v4s32_f32,      // llvm.nvvm.tex.unified.cube.grad.v4s32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_grad_v4u32_f32,      // llvm.nvvm.tex.unified.cube.grad.v4u32.f32 (IntrinsicsNVVM.td:2210)
    nvvm_tex_unified_cube_level_v4f32_f32,     // llvm.nvvm.tex.unified.cube.level.v4f32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_level_v4s32_f32,     // llvm.nvvm.tex.unified.cube.level.v4s32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_level_v4u32_f32,     // llvm.nvvm.tex.unified.cube.level.v4u32.f32 (IntrinsicsNVVM.td:2206)
    nvvm_tex_unified_cube_v4f32_f32,           // llvm.nvvm.tex.unified.cube.v4f32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_cube_v4s32_f32,           // llvm.nvvm.tex.unified.cube.v4s32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_tex_unified_cube_v4u32_f32,           // llvm.nvvm.tex.unified.cube.v4u32.f32 (IntrinsicsNVVM.td:2204)
    nvvm_texsurf_handle,                       // llvm.nvvm.texsurf.handle (IntrinsicsNVVM.td:2145)
    nvvm_texsurf_handle_internal,              // llvm.nvvm.texsurf.handle.internal (IntrinsicsNVVM.td:2147)
    nvvm_tld4_a_2d_v4f32_f32,                  // llvm.nvvm.tld4.a.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_a_2d_v4s32_f32,                  // llvm.nvvm.tld4.a.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_a_2d_v4u32_f32,                  // llvm.nvvm.tld4.a.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_b_2d_v4f32_f32,                  // llvm.nvvm.tld4.b.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_b_2d_v4s32_f32,                  // llvm.nvvm.tld4.b.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_b_2d_v4u32_f32,                  // llvm.nvvm.tld4.b.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_g_2d_v4f32_f32,                  // llvm.nvvm.tld4.g.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_g_2d_v4s32_f32,                  // llvm.nvvm.tld4.g.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_g_2d_v4u32_f32,                  // llvm.nvvm.tld4.g.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_r_2d_v4f32_f32,                  // llvm.nvvm.tld4.r.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_r_2d_v4s32_f32,                  // llvm.nvvm.tld4.r.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_r_2d_v4u32_f32,                  // llvm.nvvm.tld4.r.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_a_2d_v4f32_f32,          // llvm.nvvm.tld4.unified.a.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_a_2d_v4s32_f32,          // llvm.nvvm.tld4.unified.a.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_a_2d_v4u32_f32,          // llvm.nvvm.tld4.unified.a.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_b_2d_v4f32_f32,          // llvm.nvvm.tld4.unified.b.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_b_2d_v4s32_f32,          // llvm.nvvm.tld4.unified.b.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_b_2d_v4u32_f32,          // llvm.nvvm.tld4.unified.b.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_g_2d_v4f32_f32,          // llvm.nvvm.tld4.unified.g.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_g_2d_v4s32_f32,          // llvm.nvvm.tld4.unified.g.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_g_2d_v4u32_f32,          // llvm.nvvm.tld4.unified.g.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_r_2d_v4f32_f32,          // llvm.nvvm.tld4.unified.r.2d.v4f32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_r_2d_v4s32_f32,          // llvm.nvvm.tld4.unified.r.2d.v4s32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_tld4_unified_r_2d_v4u32_f32,          // llvm.nvvm.tld4.unified.r.2d.v4u32.f32 (IntrinsicsNVVM.td:2215)
    nvvm_trunc_d,                              // llvm.nvvm.trunc.d (IntrinsicsNVVM.td:1453)
    nvvm_trunc_f,                              // llvm.nvvm.trunc.f (IntrinsicsNVVM.td:1450)
    nvvm_trunc_ftz_f,                          // llvm.nvvm.trunc.ftz.f (IntrinsicsNVVM.td:1450)
    nvvm_txq_array_size,                       // llvm.nvvm.txq.array.size (IntrinsicsNVVM.td:2258)
    nvvm_txq_channel_data_type,                // llvm.nvvm.txq.channel.data.type (IntrinsicsNVVM.td:2258)
    nvvm_txq_channel_order,                    // llvm.nvvm.txq.channel.order (IntrinsicsNVVM.td:2258)
    nvvm_txq_depth,                            // llvm.nvvm.txq.depth (IntrinsicsNVVM.td:2258)
    nvvm_txq_height,                           // llvm.nvvm.txq.height (IntrinsicsNVVM.td:2258)
    nvvm_txq_num_mipmap_levels,                // llvm.nvvm.txq.num.mipmap.levels (IntrinsicsNVVM.td:2258)
    nvvm_txq_num_samples,                      // llvm.nvvm.txq.num.samples (IntrinsicsNVVM.td:2258)
    nvvm_txq_width,                            // llvm.nvvm.txq.width (IntrinsicsNVVM.td:2258)
    nvvm_ue8m0x2_to_bf16x2,                    // llvm.nvvm.ue8m0x2.to.bf16x2 (IntrinsicsNVVM.td:1816)
    nvvm_ui2d_rm,                              // llvm.nvvm.ui2d.rm (IntrinsicsNVVM.td:1671)
    nvvm_ui2d_rn,                              // llvm.nvvm.ui2d.rn (IntrinsicsNVVM.td:1671)
    nvvm_ui2d_rp,                              // llvm.nvvm.ui2d.rp (IntrinsicsNVVM.td:1671)
    nvvm_ui2d_rz,                              // llvm.nvvm.ui2d.rz (IntrinsicsNVVM.td:1671)
    nvvm_ui2f_rm,                              // llvm.nvvm.ui2f.rm (IntrinsicsNVVM.td:1678)
    nvvm_ui2f_rn,                              // llvm.nvvm.ui2f.rn (IntrinsicsNVVM.td:1678)
    nvvm_ui2f_rp,                              // llvm.nvvm.ui2f.rp (IntrinsicsNVVM.td:1678)
    nvvm_ui2f_rz,                              // llvm.nvvm.ui2f.rz (IntrinsicsNVVM.td:1678)
    nvvm_ull2d_rm,                             // llvm.nvvm.ull2d.rm (IntrinsicsNVVM.td:1691)
    nvvm_ull2d_rn,                             // llvm.nvvm.ull2d.rn (IntrinsicsNVVM.td:1691)
    nvvm_ull2d_rp,                             // llvm.nvvm.ull2d.rp (IntrinsicsNVVM.td:1691)
    nvvm_ull2d_rz,                             // llvm.nvvm.ull2d.rz (IntrinsicsNVVM.td:1691)
    nvvm_ull2f_rm,                             // llvm.nvvm.ull2f.rm (IntrinsicsNVVM.td:1688)
    nvvm_ull2f_rn,                             // llvm.nvvm.ull2f.rn (IntrinsicsNVVM.td:1688)
    nvvm_ull2f_rp,                             // llvm.nvvm.ull2f.rp (IntrinsicsNVVM.td:1688)
    nvvm_ull2f_rz,                             // llvm.nvvm.ull2f.rz (IntrinsicsNVVM.td:1688)
    nvvm_vote_all,                             // llvm.nvvm.vote.all (IntrinsicsNVVM.td:2446)
    nvvm_vote_all_sync,                        // llvm.nvvm.vote.all.sync (IntrinsicsNVVM.td:2456)
    nvvm_vote_any,                             // llvm.nvvm.vote.any (IntrinsicsNVVM.td:2447)
    nvvm_vote_any_sync,                        // llvm.nvvm.vote.any.sync (IntrinsicsNVVM.td:2457)
    nvvm_vote_ballot,                          // llvm.nvvm.vote.ballot (IntrinsicsNVVM.td:2449)
    nvvm_vote_ballot_sync,                     // llvm.nvvm.vote.ballot.sync (IntrinsicsNVVM.td:2459)
    nvvm_vote_uni,                             // llvm.nvvm.vote.uni (IntrinsicsNVVM.td:2448)
    nvvm_vote_uni_sync,                        // llvm.nvvm.vote.uni.sync (IntrinsicsNVVM.td:2458)
    nvvm_wgmma_commit_group_sync_aligned,      // llvm.nvvm.wgmma.commit_group.sync.aligned (IntrinsicsNVVM.td:2524)
    nvvm_wgmma_fence_sync_aligned,             // llvm.nvvm.wgmma.fence.sync.aligned (IntrinsicsNVVM.td:2521)
    nvvm_wgmma_wait_group_sync_aligned,        // llvm.nvvm.wgmma.wait_group.sync.aligned (IntrinsicsNVVM.td:2528)
    nvvm_wmma_m16n16k16_load_a_bf16_col,       // llvm.nvvm.wmma.m16n16k16.load.a.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_f16_col,        // llvm.nvvm.wmma.m16n16k16.load.a.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_s8_col,         // llvm.nvvm.wmma.m16n16k16.load.a.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_bf16_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_f16_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_s8_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_u8_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_u8_col,         // llvm.nvvm.wmma.m16n16k16.load.a.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_bf16_row,       // llvm.nvvm.wmma.m16n16k16.load.a.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_f16_row,        // llvm.nvvm.wmma.m16n16k16.load.a.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_s8_row,         // llvm.nvvm.wmma.m16n16k16.load.a.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_bf16_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_f16_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_s8_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_u8_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.a.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_a_u8_row,         // llvm.nvvm.wmma.m16n16k16.load.a.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_bf16_col,       // llvm.nvvm.wmma.m16n16k16.load.b.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_f16_col,        // llvm.nvvm.wmma.m16n16k16.load.b.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_s8_col,         // llvm.nvvm.wmma.m16n16k16.load.b.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_bf16_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_f16_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_s8_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_u8_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_u8_col,         // llvm.nvvm.wmma.m16n16k16.load.b.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_bf16_row,       // llvm.nvvm.wmma.m16n16k16.load.b.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_f16_row,        // llvm.nvvm.wmma.m16n16k16.load.b.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_s8_row,         // llvm.nvvm.wmma.m16n16k16.load.b.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_bf16_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_f16_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_s8_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_u8_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.b.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_b_u8_row,         // llvm.nvvm.wmma.m16n16k16.load.b.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f16_col,        // llvm.nvvm.wmma.m16n16k16.load.c.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f32_col,        // llvm.nvvm.wmma.m16n16k16.load.c.col.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_s32_col,        // llvm.nvvm.wmma.m16n16k16.load.c.col.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f16_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f32_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.col.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_s32_col_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.col.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f16_row,        // llvm.nvvm.wmma.m16n16k16.load.c.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f32_row,        // llvm.nvvm.wmma.m16n16k16.load.c.row.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_s32_row,        // llvm.nvvm.wmma.m16n16k16.load.c.row.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f16_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_f32_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.row.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_load_c_s32_row_stride,  // llvm.nvvm.wmma.m16n16k16.load.c.row.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k16_mma_col_col_bf16,      // llvm.nvvm.wmma.m16n16k16.mma.col.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f16_f16,   // llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f16_f32,   // llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f32_f16,   // llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f32_f32,   // llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_s8,        // llvm.nvvm.wmma.m16n16k16.mma.col.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_s8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_u8,        // llvm.nvvm.wmma.m16n16k16.mma.col.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_col_u8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_bf16,      // llvm.nvvm.wmma.m16n16k16.mma.col.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f16_f16,   // llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f16_f32,   // llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f32_f16,   // llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f32_f32,   // llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_s8,        // llvm.nvvm.wmma.m16n16k16.mma.col.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_s8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_u8,        // llvm.nvvm.wmma.m16n16k16.mma.col.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_col_row_u8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.col.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_bf16,      // llvm.nvvm.wmma.m16n16k16.mma.row.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f16_f16,   // llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f16_f32,   // llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f32_f16,   // llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f32_f32,   // llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_s8,        // llvm.nvvm.wmma.m16n16k16.mma.row.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_s8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_u8,        // llvm.nvvm.wmma.m16n16k16.mma.row.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_col_u8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_bf16,      // llvm.nvvm.wmma.m16n16k16.mma.row.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f16_f16,   // llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f16_f32,   // llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f32_f16,   // llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f32_f32,   // llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_s8,        // llvm.nvvm.wmma.m16n16k16.mma.row.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_s8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_u8,        // llvm.nvvm.wmma.m16n16k16.mma.row.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_mma_row_row_u8_satfinite,  // llvm.nvvm.wmma.m16n16k16.mma.row.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k16_store_d_f16_col,       // llvm.nvvm.wmma.m16n16k16.store.d.col.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f32_col,       // llvm.nvvm.wmma.m16n16k16.store.d.col.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_s32_col,       // llvm.nvvm.wmma.m16n16k16.store.d.col.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f16_col_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.col.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f32_col_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.col.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_s32_col_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.col.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f16_row,       // llvm.nvvm.wmma.m16n16k16.store.d.row.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f32_row,       // llvm.nvvm.wmma.m16n16k16.store.d.row.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_s32_row,       // llvm.nvvm.wmma.m16n16k16.store.d.row.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f16_row_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_f32_row_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.row.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k16_store_d_s32_row_stride,  // llvm.nvvm.wmma.m16n16k16.store.d.row.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k8_load_a_tf32_col_stride,  // llvm.nvvm.wmma.m16n16k8.load.a.col.stride.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_a_tf32_col,        // llvm.nvvm.wmma.m16n16k8.load.a.col.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_a_tf32_row_stride,  // llvm.nvvm.wmma.m16n16k8.load.a.row.stride.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_a_tf32_row,        // llvm.nvvm.wmma.m16n16k8.load.a.row.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_b_tf32_col_stride,  // llvm.nvvm.wmma.m16n16k8.load.b.col.stride.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_b_tf32_col,        // llvm.nvvm.wmma.m16n16k8.load.b.col.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_b_tf32_row_stride,  // llvm.nvvm.wmma.m16n16k8.load.b.row.stride.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_b_tf32_row,        // llvm.nvvm.wmma.m16n16k8.load.b.row.tf32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_c_f32_col,         // llvm.nvvm.wmma.m16n16k8.load.c.col.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_c_f32_col_stride,  // llvm.nvvm.wmma.m16n16k8.load.c.col.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_c_f32_row,         // llvm.nvvm.wmma.m16n16k8.load.c.row.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_load_c_f32_row_stride,  // llvm.nvvm.wmma.m16n16k8.load.c.row.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m16n16k8_mma_col_col_tf32,       // llvm.nvvm.wmma.m16n16k8.mma.col.col.tf32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k8_mma_col_row_tf32,       // llvm.nvvm.wmma.m16n16k8.mma.col.row.tf32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k8_mma_row_col_tf32,       // llvm.nvvm.wmma.m16n16k8.mma.row.col.tf32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k8_mma_row_row_tf32,       // llvm.nvvm.wmma.m16n16k8.mma.row.row.tf32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m16n16k8_store_d_f32_col,        // llvm.nvvm.wmma.m16n16k8.store.d.col.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k8_store_d_f32_col_stride,  // llvm.nvvm.wmma.m16n16k8.store.d.col.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k8_store_d_f32_row,        // llvm.nvvm.wmma.m16n16k8.store.d.row.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m16n16k8_store_d_f32_row_stride,  // llvm.nvvm.wmma.m16n16k8.store.d.row.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_load_a_bf16_col,        // llvm.nvvm.wmma.m32n8k16.load.a.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_f16_col,         // llvm.nvvm.wmma.m32n8k16.load.a.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_s8_col,          // llvm.nvvm.wmma.m32n8k16.load.a.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_bf16_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.a.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_f16_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.a.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_s8_col_stride,   // llvm.nvvm.wmma.m32n8k16.load.a.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_u8_col_stride,   // llvm.nvvm.wmma.m32n8k16.load.a.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_u8_col,          // llvm.nvvm.wmma.m32n8k16.load.a.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_bf16_row,        // llvm.nvvm.wmma.m32n8k16.load.a.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_f16_row,         // llvm.nvvm.wmma.m32n8k16.load.a.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_s8_row,          // llvm.nvvm.wmma.m32n8k16.load.a.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_bf16_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.a.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_f16_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.a.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_s8_row_stride,   // llvm.nvvm.wmma.m32n8k16.load.a.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_u8_row_stride,   // llvm.nvvm.wmma.m32n8k16.load.a.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_a_u8_row,          // llvm.nvvm.wmma.m32n8k16.load.a.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_bf16_col,        // llvm.nvvm.wmma.m32n8k16.load.b.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_f16_col,         // llvm.nvvm.wmma.m32n8k16.load.b.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_s8_col,          // llvm.nvvm.wmma.m32n8k16.load.b.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_bf16_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.b.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_f16_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.b.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_s8_col_stride,   // llvm.nvvm.wmma.m32n8k16.load.b.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_u8_col_stride,   // llvm.nvvm.wmma.m32n8k16.load.b.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_u8_col,          // llvm.nvvm.wmma.m32n8k16.load.b.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_bf16_row,        // llvm.nvvm.wmma.m32n8k16.load.b.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_f16_row,         // llvm.nvvm.wmma.m32n8k16.load.b.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_s8_row,          // llvm.nvvm.wmma.m32n8k16.load.b.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_bf16_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.b.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_f16_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.b.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_s8_row_stride,   // llvm.nvvm.wmma.m32n8k16.load.b.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_u8_row_stride,   // llvm.nvvm.wmma.m32n8k16.load.b.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_b_u8_row,          // llvm.nvvm.wmma.m32n8k16.load.b.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f16_col,         // llvm.nvvm.wmma.m32n8k16.load.c.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f32_col,         // llvm.nvvm.wmma.m32n8k16.load.c.col.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_s32_col,         // llvm.nvvm.wmma.m32n8k16.load.c.col.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f16_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f32_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.col.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_s32_col_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.col.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f16_row,         // llvm.nvvm.wmma.m32n8k16.load.c.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f32_row,         // llvm.nvvm.wmma.m32n8k16.load.c.row.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_s32_row,         // llvm.nvvm.wmma.m32n8k16.load.c.row.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f16_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_f32_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.row.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_load_c_s32_row_stride,  // llvm.nvvm.wmma.m32n8k16.load.c.row.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m32n8k16_mma_col_col_bf16,       // llvm.nvvm.wmma.m32n8k16.mma.col.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f16_f16,    // llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f16_f32,    // llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f32_f16,    // llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f32_f32,    // llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_s8,         // llvm.nvvm.wmma.m32n8k16.mma.col.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_s8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_u8,         // llvm.nvvm.wmma.m32n8k16.mma.col.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_col_u8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_bf16,       // llvm.nvvm.wmma.m32n8k16.mma.col.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f16_f16,    // llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f16_f32,    // llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f32_f16,    // llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f32_f32,    // llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_s8,         // llvm.nvvm.wmma.m32n8k16.mma.col.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_s8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_u8,         // llvm.nvvm.wmma.m32n8k16.mma.col.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_col_row_u8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.col.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_bf16,       // llvm.nvvm.wmma.m32n8k16.mma.row.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f16_f16,    // llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f16_f32,    // llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f32_f16,    // llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f32_f32,    // llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_s8,         // llvm.nvvm.wmma.m32n8k16.mma.row.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_s8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_u8,         // llvm.nvvm.wmma.m32n8k16.mma.row.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_col_u8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_bf16,       // llvm.nvvm.wmma.m32n8k16.mma.row.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f16_f16,    // llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f16_f32,    // llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f32_f16,    // llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f32_f32,    // llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_s8,         // llvm.nvvm.wmma.m32n8k16.mma.row.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_s8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_u8,         // llvm.nvvm.wmma.m32n8k16.mma.row.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_mma_row_row_u8_satfinite,  // llvm.nvvm.wmma.m32n8k16.mma.row.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m32n8k16_store_d_f16_col,        // llvm.nvvm.wmma.m32n8k16.store.d.col.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f32_col,        // llvm.nvvm.wmma.m32n8k16.store.d.col.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_s32_col,        // llvm.nvvm.wmma.m32n8k16.store.d.col.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f16_col_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.col.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f32_col_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.col.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_s32_col_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.col.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f16_row,        // llvm.nvvm.wmma.m32n8k16.store.d.row.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f32_row,        // llvm.nvvm.wmma.m32n8k16.store.d.row.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_s32_row,        // llvm.nvvm.wmma.m32n8k16.store.d.row.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f16_row_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.row.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_f32_row_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.row.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m32n8k16_store_d_s32_row_stride,  // llvm.nvvm.wmma.m32n8k16.store.d.row.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_load_a_bf16_col,        // llvm.nvvm.wmma.m8n32k16.load.a.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_f16_col,         // llvm.nvvm.wmma.m8n32k16.load.a.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_s8_col,          // llvm.nvvm.wmma.m8n32k16.load.a.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_bf16_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.a.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_f16_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.a.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_s8_col_stride,   // llvm.nvvm.wmma.m8n32k16.load.a.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_u8_col_stride,   // llvm.nvvm.wmma.m8n32k16.load.a.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_u8_col,          // llvm.nvvm.wmma.m8n32k16.load.a.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_bf16_row,        // llvm.nvvm.wmma.m8n32k16.load.a.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_f16_row,         // llvm.nvvm.wmma.m8n32k16.load.a.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_s8_row,          // llvm.nvvm.wmma.m8n32k16.load.a.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_bf16_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.a.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_f16_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.a.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_s8_row_stride,   // llvm.nvvm.wmma.m8n32k16.load.a.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_u8_row_stride,   // llvm.nvvm.wmma.m8n32k16.load.a.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_a_u8_row,          // llvm.nvvm.wmma.m8n32k16.load.a.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_bf16_col,        // llvm.nvvm.wmma.m8n32k16.load.b.col.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_f16_col,         // llvm.nvvm.wmma.m8n32k16.load.b.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_s8_col,          // llvm.nvvm.wmma.m8n32k16.load.b.col.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_bf16_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.b.col.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_f16_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.b.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_s8_col_stride,   // llvm.nvvm.wmma.m8n32k16.load.b.col.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_u8_col_stride,   // llvm.nvvm.wmma.m8n32k16.load.b.col.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_u8_col,          // llvm.nvvm.wmma.m8n32k16.load.b.col.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_bf16_row,        // llvm.nvvm.wmma.m8n32k16.load.b.row.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_f16_row,         // llvm.nvvm.wmma.m8n32k16.load.b.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_s8_row,          // llvm.nvvm.wmma.m8n32k16.load.b.row.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_bf16_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.b.row.stride.bf16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_f16_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.b.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_s8_row_stride,   // llvm.nvvm.wmma.m8n32k16.load.b.row.stride.s8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_u8_row_stride,   // llvm.nvvm.wmma.m8n32k16.load.b.row.stride.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_b_u8_row,          // llvm.nvvm.wmma.m8n32k16.load.b.row.u8 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f16_col,         // llvm.nvvm.wmma.m8n32k16.load.c.col.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f32_col,         // llvm.nvvm.wmma.m8n32k16.load.c.col.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_s32_col,         // llvm.nvvm.wmma.m8n32k16.load.c.col.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f16_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.col.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f32_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.col.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_s32_col_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.col.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f16_row,         // llvm.nvvm.wmma.m8n32k16.load.c.row.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f32_row,         // llvm.nvvm.wmma.m8n32k16.load.c.row.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_s32_row,         // llvm.nvvm.wmma.m8n32k16.load.c.row.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f16_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.row.stride.f16 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_f32_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.row.stride.f32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_load_c_s32_row_stride,  // llvm.nvvm.wmma.m8n32k16.load.c.row.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n32k16_mma_col_col_bf16,       // llvm.nvvm.wmma.m8n32k16.mma.col.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f16_f16,    // llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f16_f32,    // llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f32_f16,    // llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f32_f32,    // llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_s8,         // llvm.nvvm.wmma.m8n32k16.mma.col.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_s8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_u8,         // llvm.nvvm.wmma.m8n32k16.mma.col.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_col_u8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_bf16,       // llvm.nvvm.wmma.m8n32k16.mma.col.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f16_f16,    // llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f16_f32,    // llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f32_f16,    // llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f32_f32,    // llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_s8,         // llvm.nvvm.wmma.m8n32k16.mma.col.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_s8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_u8,         // llvm.nvvm.wmma.m8n32k16.mma.col.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_col_row_u8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.col.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_bf16,       // llvm.nvvm.wmma.m8n32k16.mma.row.col.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f16_f16,    // llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f16_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f16_f32,    // llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f16_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f32_f16,    // llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f32_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f32_f32,    // llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_f32_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_s8,         // llvm.nvvm.wmma.m8n32k16.mma.row.col.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_s8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_u8,         // llvm.nvvm.wmma.m8n32k16.mma.row.col.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_col_u8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.col.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_bf16,       // llvm.nvvm.wmma.m8n32k16.mma.row.row.bf16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f16_f16,    // llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f16_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f16_f32,    // llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f16_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.f16.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f32_f16,    // llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f16 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f32_f16_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f16.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f32_f32,    // llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f32 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_f32_f32_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.f32.f32.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_s8,         // llvm.nvvm.wmma.m8n32k16.mma.row.row.s8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_s8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.s8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_u8,         // llvm.nvvm.wmma.m8n32k16.mma.row.row.u8 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_mma_row_row_u8_satfinite,  // llvm.nvvm.wmma.m8n32k16.mma.row.row.u8.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n32k16_store_d_f16_col,        // llvm.nvvm.wmma.m8n32k16.store.d.col.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f32_col,        // llvm.nvvm.wmma.m8n32k16.store.d.col.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_s32_col,        // llvm.nvvm.wmma.m8n32k16.store.d.col.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f16_col_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.col.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f32_col_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.col.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_s32_col_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.col.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f16_row,        // llvm.nvvm.wmma.m8n32k16.store.d.row.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f32_row,        // llvm.nvvm.wmma.m8n32k16.store.d.row.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_s32_row,        // llvm.nvvm.wmma.m8n32k16.store.d.row.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f16_row_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.row.stride.f16 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_f32_row_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.row.stride.f32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n32k16_store_d_s32_row_stride,  // llvm.nvvm.wmma.m8n32k16.store.d.row.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k128_load_a_b1_row,          // llvm.nvvm.wmma.m8n8k128.load.a.row.b1 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_a_b1_row_stride,   // llvm.nvvm.wmma.m8n8k128.load.a.row.stride.b1 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_b_b1_col,          // llvm.nvvm.wmma.m8n8k128.load.b.col.b1 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_b_b1_col_stride,   // llvm.nvvm.wmma.m8n8k128.load.b.col.stride.b1 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_c_s32_col,         // llvm.nvvm.wmma.m8n8k128.load.c.col.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_c_s32_col_stride,  // llvm.nvvm.wmma.m8n8k128.load.c.col.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_c_s32_row,         // llvm.nvvm.wmma.m8n8k128.load.c.row.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_load_c_s32_row_stride,  // llvm.nvvm.wmma.m8n8k128.load.c.row.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k128_mma_and_popc_row_col_b1,  // llvm.nvvm.wmma.m8n8k128.mma.and.popc.row.col.b1 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k128_mma_xor_popc_row_col_b1,  // llvm.nvvm.wmma.m8n8k128.mma.xor.popc.row.col.b1 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k128_store_d_s32_col,        // llvm.nvvm.wmma.m8n8k128.store.d.col.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k128_store_d_s32_col_stride,  // llvm.nvvm.wmma.m8n8k128.store.d.col.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k128_store_d_s32_row,        // llvm.nvvm.wmma.m8n8k128.store.d.row.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k128_store_d_s32_row_stride,  // llvm.nvvm.wmma.m8n8k128.store.d.row.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k32_load_a_s4_row,           // llvm.nvvm.wmma.m8n8k32.load.a.row.s4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_a_s4_row_stride,    // llvm.nvvm.wmma.m8n8k32.load.a.row.stride.s4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_a_u4_row_stride,    // llvm.nvvm.wmma.m8n8k32.load.a.row.stride.u4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_a_u4_row,           // llvm.nvvm.wmma.m8n8k32.load.a.row.u4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_b_s4_col,           // llvm.nvvm.wmma.m8n8k32.load.b.col.s4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_b_s4_col_stride,    // llvm.nvvm.wmma.m8n8k32.load.b.col.stride.s4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_b_u4_col_stride,    // llvm.nvvm.wmma.m8n8k32.load.b.col.stride.u4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_b_u4_col,           // llvm.nvvm.wmma.m8n8k32.load.b.col.u4 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_c_s32_col,          // llvm.nvvm.wmma.m8n8k32.load.c.col.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_c_s32_col_stride,   // llvm.nvvm.wmma.m8n8k32.load.c.col.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_c_s32_row,          // llvm.nvvm.wmma.m8n8k32.load.c.row.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_load_c_s32_row_stride,   // llvm.nvvm.wmma.m8n8k32.load.c.row.stride.s32 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k32_mma_row_col_s4,          // llvm.nvvm.wmma.m8n8k32.mma.row.col.s4 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k32_mma_row_col_s4_satfinite,  // llvm.nvvm.wmma.m8n8k32.mma.row.col.s4.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k32_mma_row_col_u4,          // llvm.nvvm.wmma.m8n8k32.mma.row.col.u4 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k32_mma_row_col_u4_satfinite,  // llvm.nvvm.wmma.m8n8k32.mma.row.col.u4.satfinite (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k32_store_d_s32_col,         // llvm.nvvm.wmma.m8n8k32.store.d.col.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k32_store_d_s32_col_stride,  // llvm.nvvm.wmma.m8n8k32.store.d.col.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k32_store_d_s32_row,         // llvm.nvvm.wmma.m8n8k32.store.d.row.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k32_store_d_s32_row_stride,  // llvm.nvvm.wmma.m8n8k32.store.d.row.stride.s32 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k4_load_a_f64_col,           // llvm.nvvm.wmma.m8n8k4.load.a.col.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_a_f64_col_stride,    // llvm.nvvm.wmma.m8n8k4.load.a.col.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_a_f64_row,           // llvm.nvvm.wmma.m8n8k4.load.a.row.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_a_f64_row_stride,    // llvm.nvvm.wmma.m8n8k4.load.a.row.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_b_f64_col,           // llvm.nvvm.wmma.m8n8k4.load.b.col.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_b_f64_col_stride,    // llvm.nvvm.wmma.m8n8k4.load.b.col.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_b_f64_row,           // llvm.nvvm.wmma.m8n8k4.load.b.row.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_b_f64_row_stride,    // llvm.nvvm.wmma.m8n8k4.load.b.row.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_c_f64_col,           // llvm.nvvm.wmma.m8n8k4.load.c.col.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_c_f64_col_stride,    // llvm.nvvm.wmma.m8n8k4.load.c.col.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_c_f64_row,           // llvm.nvvm.wmma.m8n8k4.load.c.row.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_load_c_f64_row_stride,    // llvm.nvvm.wmma.m8n8k4.load.c.row.stride.f64 (IntrinsicsNVVM.td:2556)
    nvvm_wmma_m8n8k4_mma_col_col_f64,          // llvm.nvvm.wmma.m8n8k4.mma.col.col.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_col_rm_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.col.rm.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_col_rn_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.col.rn.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_col_rp_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.col.rp.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_col_rz_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.col.rz.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_row_f64,          // llvm.nvvm.wmma.m8n8k4.mma.col.row.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_row_rm_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.row.rm.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_row_rn_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.row.rn.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_row_rp_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.row.rp.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_col_row_rz_f64,       // llvm.nvvm.wmma.m8n8k4.mma.col.row.rz.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_col_f64,          // llvm.nvvm.wmma.m8n8k4.mma.row.col.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_col_rm_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.col.rm.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_col_rn_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.col.rn.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_col_rp_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.col.rp.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_col_rz_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.col.rz.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_row_f64,          // llvm.nvvm.wmma.m8n8k4.mma.row.row.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_row_rm_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.row.rm.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_row_rn_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.row.rn.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_row_rp_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.row.rp.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_mma_row_row_rz_f64,       // llvm.nvvm.wmma.m8n8k4.mma.row.row.rz.f64 (IntrinsicsNVVM.td:2578)
    nvvm_wmma_m8n8k4_store_d_f64_col,          // llvm.nvvm.wmma.m8n8k4.store.d.col.f64 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k4_store_d_f64_col_stride,   // llvm.nvvm.wmma.m8n8k4.store.d.col.stride.f64 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k4_store_d_f64_row,          // llvm.nvvm.wmma.m8n8k4.store.d.row.f64 (IntrinsicsNVVM.td:2560)
    nvvm_wmma_m8n8k4_store_d_f64_row_stride,   // llvm.nvvm.wmma.m8n8k4.store.d.row.stride.f64 (IntrinsicsNVVM.td:2560)
    nvvm_zext_clamp,                           // llvm.nvvm.zext.clamp (IntrinsicsNVVM.td:1630)
    nvvm_zext_wrap,                            // llvm.nvvm.zext.wrap (IntrinsicsNVVM.td:1630)
}; // enum
} // namespace llvm::Intrinsic
#endif

